src/dev/net/i8254xGBe.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * Device model for Intel's 8254x line of gigabit ethernet controllers.
  31  */
  32
  33 #ifndef __DEV_NET_I8254XGBE_HH__
  34 #define __DEV_NET_I8254XGBE_HH__
  35
  36 #include <deque>
  37 #include <string>
  38
  39 #include "base/cp_annotate.hh"
  40 #include "base/inet.hh"
  41 #include "debug/EthernetDesc.hh"
  42 #include "debug/EthernetIntr.hh"
  43 #include "dev/net/etherdevice.hh"
  44 #include "dev/net/etherint.hh"
  45 #include "dev/net/etherpkt.hh"
  46 #include "dev/net/i8254xGBe_defs.hh"
  47 #include "dev/net/pktfifo.hh"
  48 #include "dev/pci/device.hh"
  49 #include "params/IGbE.hh"
  50 #include "sim/eventq.hh"
  51
  52 class IGbEInt;
  53
  54 class IGbE : public EtherDevice
  55 {
  56   private:
  57     IGbEInt *etherInt;
  58     CPA *cpa;
  59
  60     // device registers
  61     iGbReg::Regs regs;
  62
  63     // eeprom data, status and control bits
  64     int eeOpBits, eeAddrBits, eeDataBits;
  65     uint8_t eeOpcode, eeAddr;
  66     uint16_t flash[iGbReg::EEPROM_SIZE];
  67
  68     // packet fifos
  69     PacketFifo rxFifo;
  70     PacketFifo txFifo;
  71
  72     // Packet that we are currently putting into the txFifo
  73     EthPacketPtr txPacket;
  74
  75     // Should to Rx/Tx State machine tick?
  76     bool inTick;
  77     bool rxTick;
  78     bool txTick;
  79     bool txFifoTick;
  80
  81     bool rxDmaPacket;
  82
  83     // Number of bytes copied from current RX packet
  84     unsigned pktOffset;
  85
  86     // Delays in managaging descriptors
  87     Tick fetchDelay, wbDelay;
  88     Tick fetchCompDelay, wbCompDelay;
  89     Tick rxWriteDelay, txReadDelay;
  90
  91     // Event and function to deal with RDTR timer expiring
  92     void rdtrProcess() {
  93         rxDescCache.writeback(0);
  94         DPRINTF(EthernetIntr,
  95                 "Posting RXT interrupt because RDTR timer expired\n");
  96         postInterrupt(iGbReg::IT_RXT);
  97     }
  98
  99     EventFunctionWrapper rdtrEvent;
 100
 101     // Event and function to deal with RADV timer expiring
 102     void radvProcess() {
 103         rxDescCache.writeback(0);
 104         DPRINTF(EthernetIntr,
 105                 "Posting RXT interrupt because RADV timer expired\n");
 106         postInterrupt(iGbReg::IT_RXT);
 107     }
 108
 109     EventFunctionWrapper radvEvent;
 110
 111     // Event and function to deal with TADV timer expiring
 112     void tadvProcess() {
 113         txDescCache.writeback(0);
 114         DPRINTF(EthernetIntr,
 115                 "Posting TXDW interrupt because TADV timer expired\n");
 116         postInterrupt(iGbReg::IT_TXDW);
 117     }
 118
 119     EventFunctionWrapper tadvEvent;
 120
 121     // Event and function to deal with TIDV timer expiring
 122     void tidvProcess() {
 123         txDescCache.writeback(0);
 124         DPRINTF(EthernetIntr,
 125                 "Posting TXDW interrupt because TIDV timer expired\n");
 126         postInterrupt(iGbReg::IT_TXDW);
 127     }
 128     EventFunctionWrapper tidvEvent;
 129
 130     // Main event to tick the device
 131     void tick();
 132     EventFunctionWrapper tickEvent;
 133
 134
 135     uint64_t macAddr;
 136
 137     void rxStateMachine();
 138     void txStateMachine();
 139     void txWire();
 140
 141     /** Write an interrupt into the interrupt pending register and check mask
 142      * and interrupt limit timer before sending interrupt to CPU
 143      * @param t the type of interrupt we are posting
 144      * @param now should we ignore the interrupt limiting timer
 145      */
 146     void postInterrupt(iGbReg::IntTypes t, bool now = false);
 147
 148     /** Check and see if changes to the mask register have caused an interrupt
 149      * to need to be sent or perhaps removed an interrupt cause.
 150      */
 151     void chkInterrupt();
 152
 153     /** Send an interrupt to the cpu
 154      */
 155     void delayIntEvent();
 156     void cpuPostInt();
 157     // Event to moderate interrupts
 158     EventFunctionWrapper interEvent;
 159
 160     /** Clear the interupt line to the cpu
 161      */
 162     void cpuClearInt();
 163
 164     Tick intClock() { return SimClock::Int::ns * 1024; }
 165
 166     /** This function is used to restart the clock so it can handle things like
 167      * draining and resume in one place. */
 168     void restartClock();
 169
 170     /** Check if all the draining things that need to occur have occured and
 171      * handle the drain event if so.
 172      */
 173     void checkDrain();
 174
 175     void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) {
 176         if (cpa)
 177             cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st);
 178     }
 179
 180     void anQ(std::string sm, std::string q) {
 181         if (cpa)
 182             cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 183     }
 184
 185     void anDq(std::string sm, std::string q) {
 186         if (cpa)
 187             cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 188     }
 189
 190     void anPq(std::string sm, std::string q, int num = 1) {
 191         if (cpa)
 192             cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
 193     }
 194
 195     void anRq(std::string sm, std::string q, int num = 1) {
 196         if (cpa)
 197             cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
 198     }
 199
 200     void anWe(std::string sm, std::string q) {
 201         if (cpa)
 202             cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 203     }
 204
 205     void anWf(std::string sm, std::string q) {
 206         if (cpa)
 207             cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 208     }
 209
 210
 211     template<class T>
 212     class DescCache : public Serializable
 213     {
 214       protected:
 215         virtual Addr descBase() const = 0;
 216         virtual long descHead() const = 0;
 217         virtual long descTail() const = 0;
 218         virtual long descLen() const = 0;
 219         virtual void updateHead(long h) = 0;
 220         virtual void enableSm() = 0;
 221         virtual void actionAfterWb() {}
 222         virtual void fetchAfterWb() = 0;
 223
 224         typedef std::deque<T *> CacheType;
 225         CacheType usedCache;
 226         CacheType unusedCache;
 227
 228         T *fetchBuf;
 229         T *wbBuf;
 230
 231         // Pointer to the device we cache for
 232         IGbE *igbe;
 233
 234         // Name of this  descriptor cache
 235         std::string _name;
 236
 237         // How far we've cached
 238         int cachePnt;
 239
 240         // The size of the descriptor cache
 241         int size;
 242
 243         // How many descriptors we are currently fetching
 244         int curFetching;
 245
 246         // How many descriptors we are currently writing back
 247         int wbOut;
 248
 249         // if the we wrote back to the end of the descriptor ring and are going
 250         // to have to wrap and write more
 251         bool moreToWb;
 252
 253         // What the alignment is of the next descriptor writeback
 254         Addr wbAlignment;
 255
 256         /** The packet that is currently being dmad to memory if any */
 257         EthPacketPtr pktPtr;
 258
 259         /** Shortcut for DMA address translation */
 260         Addr pciToDma(Addr a) { return igbe->pciToDma(a); }
 261
 262       public:
 263         /** Annotate sm*/
 264         std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ,
 265             annUsedDescQ, annUnusedCacheQ, annDescQ;
 266
 267         DescCache(IGbE *i, const std::string n, int s);
 268         virtual ~DescCache();
 269
 270         std::string name() { return _name; }
 271
 272         /** If the address/len/head change when we've got descriptors that are
 273          * dirty that is very bad. This function checks that we don't and if we
 274          * do panics.
 275          */
 276         void areaChanged();
 277
 278         void writeback(Addr aMask);
 279         void writeback1();
 280         EventFunctionWrapper wbDelayEvent;
 281
 282         /** Fetch a chunk of descriptors into the descriptor cache.
 283          * Calls fetchComplete when the memory system returns the data
 284          */
 285         void fetchDescriptors();
 286         void fetchDescriptors1();
 287         EventFunctionWrapper fetchDelayEvent;
 288
 289         /** Called by event when dma to read descriptors is completed
 290          */
 291         void fetchComplete();
 292         EventFunctionWrapper fetchEvent;
 293
 294         /** Called by event when dma to writeback descriptors is completed
 295          */
 296         void wbComplete();
 297         EventFunctionWrapper wbEvent;
 298
 299         /* Return the number of descriptors left in the ring, so the device has
 300          * a way to figure out if it needs to interrupt.
 301          */
 302         unsigned
 303         descLeft() const
 304         {
 305             unsigned left = unusedCache.size();
 306             if (cachePnt > descTail())
 307                 left += (descLen() - cachePnt + descTail());
 308             else
 309                 left += (descTail() - cachePnt);
 310
 311             return left;
 312         }
 313
 314         /* Return the number of descriptors used and not written back.
 315          */
 316         unsigned descUsed() const { return usedCache.size(); }
 317
 318         /* Return the number of cache unused descriptors we have. */
 319         unsigned descUnused() const { return unusedCache.size(); }
 320
 321         /* Get into a state where the descriptor address/head/etc colud be
 322          * changed */
 323         void reset();
 324
 325
 326         void serialize(CheckpointOut &cp) const override;
 327         void unserialize(CheckpointIn &cp) override;
 328
 329         virtual bool hasOutstandingEvents() {
 330             return wbEvent.scheduled() || fetchEvent.scheduled();
 331         }
 332
 333     };
 334
 335
 336     class RxDescCache : public DescCache<iGbReg::RxDesc>
 337     {
 338       protected:
 339         Addr descBase() const override { return igbe->regs.rdba(); }
 340         long descHead() const override { return igbe->regs.rdh(); }
 341         long descLen() const override { return igbe->regs.rdlen() >> 4; }
 342         long descTail() const override { return igbe->regs.rdt(); }
 343         void updateHead(long h) override { igbe->regs.rdh(h); }
 344         void enableSm() override;
 345         void fetchAfterWb() override {
 346             if (!igbe->rxTick && igbe->drainState() == DrainState::Running)
 347                 fetchDescriptors();
 348         }
 349
 350         bool pktDone;
 351
 352         /** Variable to head with header/data completion events */
 353         int splitCount;
 354
 355         /** Bytes of packet that have been copied, so we know when to
 356             set EOP */
 357         unsigned bytesCopied;
 358
 359       public:
 360         RxDescCache(IGbE *i, std::string n, int s);
 361
 362         /** Write the given packet into the buffer(s) pointed to by the
 363          * descriptor and update the book keeping. Should only be called when
 364          * there are no dma's pending.
 365          * @param packet ethernet packet to write
 366          * @param pkt_offset bytes already copied from the packet to memory
 367          * @return pkt_offset + number of bytes copied during this call
 368          */
 369         int writePacket(EthPacketPtr packet, int pkt_offset);
 370
 371         /** Called by event when dma to write packet is completed
 372          */
 373         void pktComplete();
 374
 375         /** Check if the dma on the packet has completed and RX state machine
 376          * can continue
 377          */
 378         bool packetDone();
 379
 380         EventFunctionWrapper pktEvent;
 381
 382         // Event to handle issuing header and data write at the same time
 383         // and only callking pktComplete() when both are completed
 384         void pktSplitDone();
 385         EventFunctionWrapper pktHdrEvent;
 386         EventFunctionWrapper pktDataEvent;
 387
 388         bool hasOutstandingEvents() override;
 389
 390         void serialize(CheckpointOut &cp) const override;
 391         void unserialize(CheckpointIn &cp) override;
 392     };
 393     friend class RxDescCache;
 394
 395     RxDescCache rxDescCache;
 396
 397     class TxDescCache  : public DescCache<iGbReg::TxDesc>
 398     {
 399       protected:
 400         Addr descBase() const override { return igbe->regs.tdba(); }
 401         long descHead() const override { return igbe->regs.tdh(); }
 402         long descTail() const override { return igbe->regs.tdt(); }
 403         long descLen() const override { return igbe->regs.tdlen() >> 4; }
 404         void updateHead(long h) override { igbe->regs.tdh(h); }
 405         void enableSm() override;
 406         void actionAfterWb() override;
 407         void fetchAfterWb() override {
 408             if (!igbe->txTick && igbe->drainState() == DrainState::Running)
 409                 fetchDescriptors();
 410         }
 411
 412
 413
 414         bool pktDone;
 415         bool isTcp;
 416         bool pktWaiting;
 417         bool pktMultiDesc;
 418         Addr completionAddress;
 419         bool completionEnabled;
 420         uint32_t descEnd;
 421
 422
 423         // tso variables
 424         bool useTso;
 425         Addr tsoHeaderLen;
 426         Addr tsoMss;
 427         Addr tsoTotalLen;
 428         Addr tsoUsedLen;
 429         Addr tsoPrevSeq;
 430         Addr tsoPktPayloadBytes;
 431         bool tsoLoadedHeader;
 432         bool tsoPktHasHeader;
 433         uint8_t tsoHeader[256];
 434         Addr tsoDescBytesUsed;
 435         Addr tsoCopyBytes;
 436         int tsoPkts;
 437
 438       public:
 439         TxDescCache(IGbE *i, std::string n, int s);
 440
 441         /** Tell the cache to DMA a packet from main memory into its buffer and
 442          * return the size the of the packet to reserve space in tx fifo.
 443          * @return size of the packet
 444          */
 445         unsigned getPacketSize(EthPacketPtr p);
 446         void getPacketData(EthPacketPtr p);
 447         void processContextDesc();
 448
 449         /** Return the number of dsecriptors in a cache block for threshold
 450          * operations.
 451          */
 452         unsigned
 453         descInBlock(unsigned num_desc)
 454         {
 455             return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
 456         }
 457
 458         /** Ask if the packet has been transfered so the state machine can give
 459          * it to the fifo.
 460          * @return packet available in descriptor cache
 461          */
 462         bool packetAvailable();
 463
 464         /** Ask if we are still waiting for the packet to be transfered.
 465          * @return packet still in transit.
 466          */
 467         bool packetWaiting() { return pktWaiting; }
 468
 469         /** Ask if this packet is composed of multiple descriptors
 470          * so even if we've got data, we need to wait for more before
 471          * we can send it out.
 472          * @return packet can't be sent out because it's a multi-descriptor
 473          * packet
 474          */
 475         bool packetMultiDesc() { return pktMultiDesc;}
 476
 477         /** Called by event when dma to write packet is completed
 478          */
 479         void pktComplete();
 480         EventFunctionWrapper pktEvent;
 481
 482         void headerComplete();
 483         EventFunctionWrapper headerEvent;
 484
 485
 486         void completionWriteback(Addr a, bool enabled) {
 487             DPRINTF(EthernetDesc,
 488                     "Completion writeback Addr: %#x enabled: %d\n",
 489                     a, enabled);
 490             completionAddress = a;
 491             completionEnabled = enabled;
 492         }
 493
 494         bool hasOutstandingEvents() override;
 495
 496         void nullCallback() {
 497             DPRINTF(EthernetDesc, "Completion writeback complete\n");
 498         }
 499         EventFunctionWrapper nullEvent;
 500
 501         void serialize(CheckpointOut &cp) const override;
 502         void unserialize(CheckpointIn &cp) override;
 503     };
 504
 505     friend class TxDescCache;
 506
 507     TxDescCache txDescCache;
 508
 509   public:
 510     typedef IGbEParams Params;
 511     const Params *
 512     params() const {
 513         return dynamic_cast<const Params *>(_params);
 514     }
 515
 516     IGbE(const Params *params);
 517     ~IGbE();
 518     void init() override;
 519
 520     Port &getPort(const std::string &if_name,
 521                   PortID idx=InvalidPortID) override;
 522
 523     Tick lastInterrupt;
 524
 525     Tick read(PacketPtr pkt) override;
 526     Tick write(PacketPtr pkt) override;
 527
 528     Tick writeConfig(PacketPtr pkt) override;
 529
 530     bool ethRxPkt(EthPacketPtr packet);
 531     void ethTxDone();
 532
 533     void serialize(CheckpointOut &cp) const override;
 534     void unserialize(CheckpointIn &cp) override;
 535
 536     DrainState drain() override;
 537     void drainResume() override;
 538
 539 };
 540
 541 class IGbEInt : public EtherInt
 542 {
 543   private:
 544     IGbE *dev;
 545
 546   public:
 547     IGbEInt(const std::string &name, IGbE *d)
 548         : EtherInt(name), dev(d)
 549     { }
 550
 551     virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
 552     virtual void sendDone() { dev->ethTxDone(); }
 553 };
 554
 555 #endif //__DEV_NET_I8254XGBE_HH__