src/dev/ns_gige.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Nathan Binkert
  29  *          Lisa Hsu
  30  */
  31
  32 /** @file
  33  * Device module for modelling the National Semiconductor
  34  * DP83820 ethernet controller
  35  */
  36
  37 #ifndef __DEV_NS_GIGE_HH__
  38 #define __DEV_NS_GIGE_HH__
  39
  40 #include "base/inet.hh"
  41 #include "base/statistics.hh"
  42 #include "dev/etherint.hh"
  43 #include "dev/etherpkt.hh"
  44 #include "dev/io_device.hh"
  45 #include "dev/ns_gige_reg.h"
  46 #include "dev/pcidev.hh"
  47 #include "dev/pktfifo.hh"
  48 #include "sim/eventq.hh"
  49
  50 // Hash filtering constants
  51 const uint16_t FHASH_ADDR  = 0x100;
  52 const uint16_t FHASH_SIZE  = 0x100;
  53
  54 // EEPROM constants
  55 const uint8_t  EEPROM_READ = 0x2;
  56 const uint8_t  EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
  57 const uint8_t  EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
  58 const uint8_t  EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
  59 const uint8_t  EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
  60
  61 /**
  62  * Ethernet device registers
  63  */
  64 struct dp_regs {
  65     uint32_t    command;
  66     uint32_t    config;
  67     uint32_t    mear;
  68     uint32_t    ptscr;
  69     uint32_t    isr;
  70     uint32_t    imr;
  71     uint32_t    ier;
  72     uint32_t    ihr;
  73     uint32_t    txdp;
  74     uint32_t    txdp_hi;
  75     uint32_t    txcfg;
  76     uint32_t    gpior;
  77     uint32_t    rxdp;
  78     uint32_t    rxdp_hi;
  79     uint32_t    rxcfg;
  80     uint32_t    pqcr;
  81     uint32_t    wcsr;
  82     uint32_t    pcr;
  83     uint32_t    rfcr;
  84     uint32_t    rfdr;
  85     uint32_t    brar;
  86     uint32_t    brdr;
  87     uint32_t    srr;
  88     uint32_t    mibc;
  89     uint32_t    vrcr;
  90     uint32_t    vtcr;
  91     uint32_t    vdr;
  92     uint32_t    ccsr;
  93     uint32_t    tbicr;
  94     uint32_t    tbisr;
  95     uint32_t    tanar;
  96     uint32_t    tanlpar;
  97     uint32_t    taner;
  98     uint32_t    tesr;
  99 };
 100
 101 struct dp_rom {
 102     /**
 103      * for perfect match memory.
 104      * the linux driver doesn't use any other ROM
 105      */
 106     uint8_t perfectMatch[ETH_ADDR_LEN];
 107
 108     /**
 109      * for hash table memory.
 110      * used by the freebsd driver
 111      */
 112     uint8_t filterHash[FHASH_SIZE];
 113 };
 114
 115 class NSGigEInt;
 116 class Packet;
 117
 118 /**
 119  * NS DP83820 Ethernet device model
 120  */
 121 class NSGigE : public PciDev
 122 {
 123   public:
 124     /** Transmit State Machine states */
 125     enum TxState
 126     {
 127         txIdle,
 128         txDescRefr,
 129         txDescRead,
 130         txFifoBlock,
 131         txFragRead,
 132         txDescWrite,
 133         txAdvance
 134     };
 135
 136     /** Receive State Machine States */
 137     enum RxState
 138     {
 139         rxIdle,
 140         rxDescRefr,
 141         rxDescRead,
 142         rxFifoBlock,
 143         rxFragWrite,
 144         rxDescWrite,
 145         rxAdvance
 146     };
 147
 148     enum DmaState
 149     {
 150         dmaIdle,
 151         dmaReading,
 152         dmaWriting,
 153         dmaReadWaiting,
 154         dmaWriteWaiting
 155     };
 156
 157     /** EEPROM State Machine States */
 158     enum EEPROMState
 159     {
 160         eepromStart,
 161         eepromGetOpcode,
 162         eepromGetAddress,
 163         eepromRead
 164     };
 165
 166   protected:
 167     /** device register file */
 168     dp_regs regs;
 169     dp_rom rom;
 170
 171     /** pci settings */
 172     bool ioEnable;
 173 #if 0
 174     bool memEnable;
 175     bool bmEnable;
 176 #endif
 177
 178     /*** BASIC STRUCTURES FOR TX/RX ***/
 179     /* Data FIFOs */
 180     PacketFifo txFifo;
 181     PacketFifo rxFifo;
 182
 183     /** various helper vars */
 184     EthPacketPtr txPacket;
 185     EthPacketPtr rxPacket;
 186     uint8_t *txPacketBufPtr;
 187     uint8_t *rxPacketBufPtr;
 188     uint32_t txXferLen;
 189     uint32_t rxXferLen;
 190     bool rxDmaFree;
 191     bool txDmaFree;
 192
 193     /** DescCaches */
 194     ns_desc32 txDesc32;
 195     ns_desc32 rxDesc32;
 196     ns_desc64 txDesc64;
 197     ns_desc64 rxDesc64;
 198
 199     /* state machine cycle time */
 200     Tick clock;
 201     inline Tick cycles(int numCycles) const { return numCycles * clock; }
 202
 203     /* tx State Machine */
 204     TxState txState;
 205     bool txEnable;
 206
 207     /** Current Transmit Descriptor Done */
 208     bool CTDD;
 209     /** halt the tx state machine after next packet */
 210     bool txHalt;
 211     /** ptr to the next byte in the current fragment */
 212     Addr txFragPtr;
 213     /** count of bytes remaining in the current descriptor */
 214     uint32_t txDescCnt;
 215     DmaState txDmaState;
 216
 217     /** rx State Machine */
 218     RxState rxState;
 219     bool rxEnable;
 220
 221     /** Current Receive Descriptor Done */
 222     bool CRDD;
 223     /** num of bytes in the current packet being drained from rxDataFifo */
 224     uint32_t rxPktBytes;
 225     /** halt the rx state machine after current packet */
 226     bool rxHalt;
 227     /** ptr to the next byte in current fragment */
 228     Addr rxFragPtr;
 229     /** count of bytes remaining in the current descriptor */
 230     uint32_t rxDescCnt;
 231     DmaState rxDmaState;
 232
 233     bool extstsEnable;
 234
 235     /** EEPROM State Machine */
 236     EEPROMState eepromState;
 237     bool eepromClk;
 238     uint8_t eepromBitsToRx;
 239     uint8_t eepromOpcode;
 240     uint8_t eepromAddress;
 241     uint16_t eepromData;
 242
 243   protected:
 244     Tick dmaReadDelay;
 245     Tick dmaWriteDelay;
 246
 247     Tick dmaReadFactor;
 248     Tick dmaWriteFactor;
 249
 250     void *rxDmaData;
 251     Addr  rxDmaAddr;
 252     int   rxDmaLen;
 253     bool  doRxDmaRead();
 254     bool  doRxDmaWrite();
 255
 256     void *txDmaData;
 257     Addr  txDmaAddr;
 258     int   txDmaLen;
 259     bool  doTxDmaRead();
 260     bool  doTxDmaWrite();
 261
 262     void rxDmaReadDone();
 263     friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
 264     EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
 265
 266     void rxDmaWriteDone();
 267     friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
 268     EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
 269
 270     void txDmaReadDone();
 271     friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
 272     EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
 273
 274     void txDmaWriteDone();
 275     friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
 276     EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
 277
 278     bool dmaDescFree;
 279     bool dmaDataFree;
 280
 281   protected:
 282     Tick txDelay;
 283     Tick rxDelay;
 284
 285     void txReset();
 286     void rxReset();
 287     void regsReset();
 288
 289     void rxKick();
 290     Tick rxKickTick;
 291     typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
 292     friend void RxKickEvent::process();
 293     RxKickEvent rxKickEvent;
 294
 295     void txKick();
 296     Tick txKickTick;
 297     typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
 298     friend void TxKickEvent::process();
 299     TxKickEvent txKickEvent;
 300
 301     void eepromKick();
 302
 303     /**
 304      * Retransmit event
 305      */
 306     void transmit();
 307     void txEventTransmit()
 308     {
 309         transmit();
 310         if (txState == txFifoBlock)
 311             txKick();
 312     }
 313     typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
 314     friend void TxEvent::process();
 315     TxEvent txEvent;
 316
 317     void txDump() const;
 318     void rxDump() const;
 319
 320     /**
 321      * receive address filter
 322      */
 323     bool rxFilterEnable;
 324     bool rxFilter(const EthPacketPtr &packet);
 325     bool acceptBroadcast;
 326     bool acceptMulticast;
 327     bool acceptUnicast;
 328     bool acceptPerfect;
 329     bool acceptArp;
 330     bool multicastHashEnable;
 331
 332     /**
 333      * Interrupt management
 334      */
 335     void devIntrPost(uint32_t interrupts);
 336     void devIntrClear(uint32_t interrupts);
 337     void devIntrChangeMask();
 338
 339     Tick intrDelay;
 340     Tick intrTick;
 341     bool cpuPendingIntr;
 342     void cpuIntrPost(Tick when);
 343     void cpuInterrupt();
 344     void cpuIntrClear();
 345
 346     typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
 347     friend void IntrEvent::process();
 348     IntrEvent *intrEvent;
 349     NSGigEInt *interface;
 350
 351   public:
 352     struct Params : public PciDev::Params
 353     {
 354         Tick clock;
 355         Tick intr_delay;
 356         Tick tx_delay;
 357         Tick rx_delay;
 358         bool dma_desc_free;
 359         bool dma_data_free;
 360         Tick dma_read_delay;
 361         Tick dma_write_delay;
 362         Tick dma_read_factor;
 363         Tick dma_write_factor;
 364         bool rx_filter;
 365         Net::EthAddr eaddr;
 366         uint32_t tx_fifo_size;
 367         uint32_t rx_fifo_size;
 368         bool rx_thread;
 369         bool tx_thread;
 370         bool rss;
 371         bool dma_no_allocate;
 372     };
 373
 374     NSGigE(Params *params);
 375     ~NSGigE();
 376     const Params *params() const { return (const Params *)_params; }
 377
 378     virtual Tick writeConfig(Packet *pkt);
 379
 380     virtual Tick read(Packet *pkt);
 381     virtual Tick write(Packet *pkt);
 382
 383     bool cpuIntrPending() const;
 384     void cpuIntrAck() { cpuIntrClear(); }
 385
 386     bool recvPacket(EthPacketPtr packet);
 387     void transferDone();
 388
 389     void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
 390
 391     virtual void serialize(std::ostream &os);
 392     virtual void unserialize(Checkpoint *cp, const std::string &section);
 393
 394     virtual void resume();
 395
 396   public:
 397     void regStats();
 398
 399   private:
 400     Stats::Scalar<> txBytes;
 401     Stats::Scalar<> rxBytes;
 402     Stats::Scalar<> txPackets;
 403     Stats::Scalar<> rxPackets;
 404     Stats::Scalar<> txIpChecksums;
 405     Stats::Scalar<> rxIpChecksums;
 406     Stats::Scalar<> txTcpChecksums;
 407     Stats::Scalar<> rxTcpChecksums;
 408     Stats::Scalar<> txUdpChecksums;
 409     Stats::Scalar<> rxUdpChecksums;
 410     Stats::Scalar<> descDmaReads;
 411     Stats::Scalar<> descDmaWrites;
 412     Stats::Scalar<> descDmaRdBytes;
 413     Stats::Scalar<> descDmaWrBytes;
 414     Stats::Formula totBandwidth;
 415     Stats::Formula totPackets;
 416     Stats::Formula totBytes;
 417     Stats::Formula totPacketRate;
 418     Stats::Formula txBandwidth;
 419     Stats::Formula rxBandwidth;
 420     Stats::Formula txPacketRate;
 421     Stats::Formula rxPacketRate;
 422     Stats::Scalar<> postedSwi;
 423     Stats::Formula coalescedSwi;
 424     Stats::Scalar<> totalSwi;
 425     Stats::Scalar<> postedRxIdle;
 426     Stats::Formula coalescedRxIdle;
 427     Stats::Scalar<> totalRxIdle;
 428     Stats::Scalar<> postedRxOk;
 429     Stats::Formula coalescedRxOk;
 430     Stats::Scalar<> totalRxOk;
 431     Stats::Scalar<> postedRxDesc;
 432     Stats::Formula coalescedRxDesc;
 433     Stats::Scalar<> totalRxDesc;
 434     Stats::Scalar<> postedTxOk;
 435     Stats::Formula coalescedTxOk;
 436     Stats::Scalar<> totalTxOk;
 437     Stats::Scalar<> postedTxIdle;
 438     Stats::Formula coalescedTxIdle;
 439     Stats::Scalar<> totalTxIdle;
 440     Stats::Scalar<> postedTxDesc;
 441     Stats::Formula coalescedTxDesc;
 442     Stats::Scalar<> totalTxDesc;
 443     Stats::Scalar<> postedRxOrn;
 444     Stats::Formula coalescedRxOrn;
 445     Stats::Scalar<> totalRxOrn;
 446     Stats::Formula coalescedTotal;
 447     Stats::Scalar<> postedInterrupts;
 448     Stats::Scalar<> droppedPackets;
 449 };
 450
 451 /*
 452  * Ethernet Interface for an Ethernet Device
 453  */
 454 class NSGigEInt : public EtherInt
 455 {
 456   private:
 457     NSGigE *dev;
 458
 459   public:
 460     NSGigEInt(const std::string &name, NSGigE *d)
 461         : EtherInt(name), dev(d) { dev->setInterface(this); }
 462
 463     virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
 464     virtual void sendDone() { dev->transferDone(); }
 465 };
 466
 467 #endif // __DEV_NS_GIGE_HH__