2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
33 * Device module for modelling the National Semiconductor
34 * DP83820 ethernet controller
37 #ifndef __DEV_NS_GIGE_HH__
38 #define __DEV_NS_GIGE_HH__
40 #include "base/inet.hh"
41 #include "base/statistics.hh"
42 #include "dev/etherint.hh"
43 #include "dev/etherpkt.hh"
44 #include "dev/io_device.hh"
45 #include "dev/ns_gige_reg.h"
46 #include "dev/pcidev.hh"
47 #include "dev/pktfifo.hh"
48 #include "params/NSGigE.hh"
49 #include "sim/eventq.hh"
51 // Hash filtering constants
52 const uint16_t FHASH_ADDR = 0x100;
53 const uint16_t FHASH_SIZE = 0x100;
56 const uint8_t EEPROM_READ = 0x2;
57 const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
58 const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
59 const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
60 const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
63 * Ethernet device registers
104 * for perfect match memory.
105 * the linux driver doesn't use any other ROM
107 uint8_t perfectMatch[ETH_ADDR_LEN];
110 * for hash table memory.
111 * used by the freebsd driver
113 uint8_t filterHash[FHASH_SIZE];
120 * NS DP83820 Ethernet device model
122 class NSGigE : public PciDev
125 /** Transmit State Machine states */
137 /** Receive State Machine States */
158 /** EEPROM State Machine States */
168 /** device register file */
179 /*** BASIC STRUCTURES FOR TX/RX ***/
184 /** various helper vars */
185 EthPacketPtr txPacket;
186 EthPacketPtr rxPacket;
187 uint8_t *txPacketBufPtr;
188 uint8_t *rxPacketBufPtr;
200 /* state machine cycle time */
202 inline Tick cycles(int numCycles) const { return numCycles * clock; }
204 /* tx State Machine */
208 /** Current Transmit Descriptor Done */
210 /** halt the tx state machine after next packet */
212 /** ptr to the next byte in the current fragment */
214 /** count of bytes remaining in the current descriptor */
218 /** rx State Machine */
222 /** Current Receive Descriptor Done */
224 /** num of bytes in the current packet being drained from rxDataFifo */
226 /** halt the rx state machine after current packet */
228 /** ptr to the next byte in current fragment */
230 /** count of bytes remaining in the current descriptor */
236 /** EEPROM State Machine */
237 EEPROMState eepromState;
239 uint8_t eepromBitsToRx;
240 uint8_t eepromOpcode;
241 uint8_t eepromAddress;
263 void rxDmaReadDone();
264 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
265 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
267 void rxDmaWriteDone();
268 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
269 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
271 void txDmaReadDone();
272 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
273 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
275 void txDmaWriteDone();
276 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
277 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
292 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
293 friend void RxKickEvent::process();
294 RxKickEvent rxKickEvent;
298 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
299 friend void TxKickEvent::process();
300 TxKickEvent txKickEvent;
308 void txEventTransmit()
311 if (txState == txFifoBlock)
314 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
315 friend void TxEvent::process();
322 * receive address filter
325 bool rxFilter(const EthPacketPtr &packet);
326 bool acceptBroadcast;
327 bool acceptMulticast;
331 bool multicastHashEnable;
334 * Interrupt management
336 void devIntrPost(uint32_t interrupts);
337 void devIntrClear(uint32_t interrupts);
338 void devIntrChangeMask();
343 void cpuIntrPost(Tick when);
347 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
348 friend void IntrEvent::process();
349 IntrEvent *intrEvent;
350 NSGigEInt *interface;
353 typedef NSGigEParams Params;
354 const Params *params() const { return (const Params *)_params; }
355 NSGigE(Params *params);
358 virtual Tick writeConfig(PacketPtr pkt);
360 virtual Tick read(PacketPtr pkt);
361 virtual Tick write(PacketPtr pkt);
363 bool cpuIntrPending() const;
364 void cpuIntrAck() { cpuIntrClear(); }
366 bool recvPacket(EthPacketPtr packet);
369 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
371 virtual void serialize(std::ostream &os);
372 virtual void unserialize(Checkpoint *cp, const std::string §ion);
374 virtual void resume();
380 Stats::Scalar<> txBytes;
381 Stats::Scalar<> rxBytes;
382 Stats::Scalar<> txPackets;
383 Stats::Scalar<> rxPackets;
384 Stats::Scalar<> txIpChecksums;
385 Stats::Scalar<> rxIpChecksums;
386 Stats::Scalar<> txTcpChecksums;
387 Stats::Scalar<> rxTcpChecksums;
388 Stats::Scalar<> txUdpChecksums;
389 Stats::Scalar<> rxUdpChecksums;
390 Stats::Scalar<> descDmaReads;
391 Stats::Scalar<> descDmaWrites;
392 Stats::Scalar<> descDmaRdBytes;
393 Stats::Scalar<> descDmaWrBytes;
394 Stats::Formula totBandwidth;
395 Stats::Formula totPackets;
396 Stats::Formula totBytes;
397 Stats::Formula totPacketRate;
398 Stats::Formula txBandwidth;
399 Stats::Formula rxBandwidth;
400 Stats::Formula txPacketRate;
401 Stats::Formula rxPacketRate;
402 Stats::Scalar<> postedSwi;
403 Stats::Formula coalescedSwi;
404 Stats::Scalar<> totalSwi;
405 Stats::Scalar<> postedRxIdle;
406 Stats::Formula coalescedRxIdle;
407 Stats::Scalar<> totalRxIdle;
408 Stats::Scalar<> postedRxOk;
409 Stats::Formula coalescedRxOk;
410 Stats::Scalar<> totalRxOk;
411 Stats::Scalar<> postedRxDesc;
412 Stats::Formula coalescedRxDesc;
413 Stats::Scalar<> totalRxDesc;
414 Stats::Scalar<> postedTxOk;
415 Stats::Formula coalescedTxOk;
416 Stats::Scalar<> totalTxOk;
417 Stats::Scalar<> postedTxIdle;
418 Stats::Formula coalescedTxIdle;
419 Stats::Scalar<> totalTxIdle;
420 Stats::Scalar<> postedTxDesc;
421 Stats::Formula coalescedTxDesc;
422 Stats::Scalar<> totalTxDesc;
423 Stats::Scalar<> postedRxOrn;
424 Stats::Formula coalescedRxOrn;
425 Stats::Scalar<> totalRxOrn;
426 Stats::Formula coalescedTotal;
427 Stats::Scalar<> postedInterrupts;
428 Stats::Scalar<> droppedPackets;
432 * Ethernet Interface for an Ethernet Device
434 class NSGigEInt : public EtherInt
440 NSGigEInt(const std::string &name, NSGigE *d)
441 : EtherInt(name), dev(d) { dev->setInterface(this); }
443 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
444 virtual void sendDone() { dev->transferDone(); }
447 #endif // __DEV_NS_GIGE_HH__