2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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32 * Device module for modelling the National Semiconductor
33 * DP83820 ethernet controller
36 #ifndef __DEV_NS_GIGE_HH__
37 #define __DEV_NS_GIGE_HH__
39 #include "base/inet.hh"
40 #include "base/statistics.hh"
41 #include "dev/etherint.hh"
42 #include "dev/etherpkt.hh"
43 #include "dev/io_device.hh"
44 #include "dev/ns_gige_reg.h"
45 #include "dev/pcidev.hh"
46 #include "dev/pktfifo.hh"
47 #include "sim/eventq.hh"
49 // Hash filtering constants
50 const uint16_t FHASH_ADDR = 0x100;
51 const uint16_t FHASH_SIZE = 0x100;
54 const uint8_t EEPROM_READ = 0x2;
55 const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
56 const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
57 const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
58 const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
61 * Ethernet device registers
102 * for perfect match memory.
103 * the linux driver doesn't use any other ROM
105 uint8_t perfectMatch[ETH_ADDR_LEN];
108 * for hash table memory.
109 * used by the freebsd driver
111 uint8_t filterHash[FHASH_SIZE];
119 * NS DP83820 Ethernet device model
121 class NSGigE : public PciDev
124 /** Transmit State Machine states */
136 /** Receive State Machine States */
157 /** EEPROM State Machine States */
167 /** device register file */
178 /*** BASIC STRUCTURES FOR TX/RX ***/
183 /** various helper vars */
184 EthPacketPtr txPacket;
185 EthPacketPtr rxPacket;
186 uint8_t *txPacketBufPtr;
187 uint8_t *rxPacketBufPtr;
199 /* state machine cycle time */
201 inline Tick cycles(int numCycles) const { return numCycles * clock; }
203 /* tx State Machine */
207 /** Current Transmit Descriptor Done */
209 /** halt the tx state machine after next packet */
211 /** ptr to the next byte in the current fragment */
213 /** count of bytes remaining in the current descriptor */
217 /** rx State Machine */
221 /** Current Receive Descriptor Done */
223 /** num of bytes in the current packet being drained from rxDataFifo */
225 /** halt the rx state machine after current packet */
227 /** ptr to the next byte in current fragment */
229 /** count of bytes remaining in the current descriptor */
235 /** EEPROM State Machine */
236 EEPROMState eepromState;
238 uint8_t eepromBitsToRx;
239 uint8_t eepromOpcode;
240 uint8_t eepromAddress;
262 void rxDmaReadDone();
263 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
264 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
266 void rxDmaWriteDone();
267 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
268 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
270 void txDmaReadDone();
271 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
272 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
274 void txDmaWriteDone();
275 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
276 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
291 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
292 friend void RxKickEvent::process();
293 RxKickEvent rxKickEvent;
297 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
298 friend void TxKickEvent::process();
299 TxKickEvent txKickEvent;
307 void txEventTransmit()
310 if (txState == txFifoBlock)
313 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
314 friend void TxEvent::process();
321 * receive address filter
324 bool rxFilter(const EthPacketPtr &packet);
325 bool acceptBroadcast;
326 bool acceptMulticast;
330 bool multicastHashEnable;
333 * Interrupt management
335 void devIntrPost(uint32_t interrupts);
336 void devIntrClear(uint32_t interrupts);
337 void devIntrChangeMask();
342 void cpuIntrPost(Tick when);
346 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
347 friend void IntrEvent::process();
348 IntrEvent *intrEvent;
349 NSGigEInt *interface;
352 struct Params : public PciDev::Params
361 Tick dma_write_delay;
362 Tick dma_read_factor;
363 Tick dma_write_factor;
366 uint32_t tx_fifo_size;
367 uint32_t rx_fifo_size;
371 bool dma_no_allocate;
374 NSGigE(Params *params);
376 const Params *params() const { return (const Params *)_params; }
378 virtual void writeConfig(int offset, const uint16_t data);
380 virtual Tick read(Packet *pkt);
381 virtual Tick write(Packet *pkt);
383 bool cpuIntrPending() const;
384 void cpuIntrAck() { cpuIntrClear(); }
386 bool recvPacket(EthPacketPtr packet);
389 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
391 virtual void serialize(std::ostream &os);
392 virtual void unserialize(Checkpoint *cp, const std::string §ion);
398 Stats::Scalar<> txBytes;
399 Stats::Scalar<> rxBytes;
400 Stats::Scalar<> txPackets;
401 Stats::Scalar<> rxPackets;
402 Stats::Scalar<> txIpChecksums;
403 Stats::Scalar<> rxIpChecksums;
404 Stats::Scalar<> txTcpChecksums;
405 Stats::Scalar<> rxTcpChecksums;
406 Stats::Scalar<> txUdpChecksums;
407 Stats::Scalar<> rxUdpChecksums;
408 Stats::Scalar<> descDmaReads;
409 Stats::Scalar<> descDmaWrites;
410 Stats::Scalar<> descDmaRdBytes;
411 Stats::Scalar<> descDmaWrBytes;
412 Stats::Formula totBandwidth;
413 Stats::Formula totPackets;
414 Stats::Formula totBytes;
415 Stats::Formula totPacketRate;
416 Stats::Formula txBandwidth;
417 Stats::Formula rxBandwidth;
418 Stats::Formula txPacketRate;
419 Stats::Formula rxPacketRate;
420 Stats::Scalar<> postedSwi;
421 Stats::Formula coalescedSwi;
422 Stats::Scalar<> totalSwi;
423 Stats::Scalar<> postedRxIdle;
424 Stats::Formula coalescedRxIdle;
425 Stats::Scalar<> totalRxIdle;
426 Stats::Scalar<> postedRxOk;
427 Stats::Formula coalescedRxOk;
428 Stats::Scalar<> totalRxOk;
429 Stats::Scalar<> postedRxDesc;
430 Stats::Formula coalescedRxDesc;
431 Stats::Scalar<> totalRxDesc;
432 Stats::Scalar<> postedTxOk;
433 Stats::Formula coalescedTxOk;
434 Stats::Scalar<> totalTxOk;
435 Stats::Scalar<> postedTxIdle;
436 Stats::Formula coalescedTxIdle;
437 Stats::Scalar<> totalTxIdle;
438 Stats::Scalar<> postedTxDesc;
439 Stats::Formula coalescedTxDesc;
440 Stats::Scalar<> totalTxDesc;
441 Stats::Scalar<> postedRxOrn;
442 Stats::Formula coalescedRxOrn;
443 Stats::Scalar<> totalRxOrn;
444 Stats::Formula coalescedTotal;
445 Stats::Scalar<> postedInterrupts;
446 Stats::Scalar<> droppedPackets;
450 * Ethernet Interface for an Ethernet Device
452 class NSGigEInt : public EtherInt
458 NSGigEInt(const std::string &name, NSGigE *d)
459 : EtherInt(name), dev(d) { dev->setInterface(this); }
461 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
462 virtual void sendDone() { dev->transferDone(); }
465 #endif // __DEV_NS_GIGE_HH__