src/dev/pci/CopyEngine.py

   1 # Copyright (c) 2008 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26
  27 from m5.SimObject import SimObject
  28 from m5.params import *
  29 from m5.proxy import *
  30
  31 from m5.objects.PciDevice import PciDevice, PciMemBar
  32
  33 class CopyEngine(PciDevice):
  34     type = 'CopyEngine'
  35     cxx_header = "dev/pci/copy_engine.hh"
  36     dma = VectorRequestPort("Copy engine DMA port")
  37     VendorID = 0x8086
  38     DeviceID = 0x1a38
  39     Revision = 0xA2 # CM2 stepping (newest listed)
  40     SubsystemID = 0
  41     SubsystemVendorID = 0
  42     Status = 0x0000
  43     SubClassCode = 0x08
  44     ClassCode = 0x80
  45     ProgIF = 0x00
  46     MaximumLatency = 0x00
  47     MinimumGrant = 0xff
  48     InterruptLine = 0x20
  49     InterruptPin = 0x01
  50
  51     BAR0 = PciMemBar(size='1KiB')
  52
  53     ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
  54     XferCap = Param.MemorySize('4KiB',
  55             "Number of bits of transfer size that are supported")
  56
  57     latBeforeBegin = Param.Latency('20ns',
  58             "Latency after a DMA command is seen before it's proccessed")
  59     latAfterCompletion = Param.Latency('20ns',
  60             "Latency after a DMA command is complete before "
  61             "it's reported as such")
  62
  63