src/dev/pci/copy_engine.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2008 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /* @file
  42  * Device model for Intel's I/O Acceleration Technology (I/OAT).
  43  * A DMA asyncronous copy engine
  44  */
  45
  46 #ifndef __DEV_PCI_COPY_ENGINE_HH__
  47 #define __DEV_PCI_COPY_ENGINE_HH__
  48
  49 #include <vector>
  50
  51 #include "base/statistics.hh"
  52 #include "dev/pci/copy_engine_defs.hh"
  53 #include "dev/pci/device.hh"
  54 #include "params/CopyEngine.hh"
  55 #include "sim/drain.hh"
  56 #include "sim/eventq.hh"
  57
  58 class CopyEngine : public PciDevice
  59 {
  60     class CopyEngineChannel : public Drainable, public Serializable
  61     {
  62       private:
  63         DmaPort cePort;
  64         CopyEngine *ce;
  65         CopyEngineReg::ChanRegs  cr;
  66         int channelId;
  67         CopyEngineReg::DmaDesc *curDmaDesc;
  68         uint8_t *copyBuffer;
  69
  70         bool busy;
  71         bool underReset;
  72         bool refreshNext;
  73         Addr lastDescriptorAddr;
  74         Addr fetchAddress;
  75
  76         Tick latBeforeBegin;
  77         Tick latAfterCompletion;
  78
  79         uint64_t completionDataReg;
  80
  81         enum ChannelState {
  82             Idle,
  83             AddressFetch,
  84             DescriptorFetch,
  85             DMARead,
  86             DMAWrite,
  87             CompletionWrite
  88         };
  89
  90         ChannelState nextState;
  91
  92       public:
  93         CopyEngineChannel(CopyEngine *_ce, int cid);
  94         virtual ~CopyEngineChannel();
  95         Port &getPort();
  96
  97         std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
  98         virtual Tick read(PacketPtr pkt)
  99                         { panic("CopyEngineChannel has no I/O access\n");}
 100         virtual Tick write(PacketPtr pkt)
 101                         { panic("CopyEngineChannel has no I/O access\n"); }
 102
 103         void channelRead(PacketPtr pkt, Addr daddr, int size);
 104         void channelWrite(PacketPtr pkt, Addr daddr, int size);
 105
 106         DrainState drain() override;
 107         void drainResume() override;
 108
 109         void serialize(CheckpointOut &cp) const override;
 110         void unserialize(CheckpointIn &cp) override;
 111
 112       private:
 113         void fetchDescriptor(Addr address);
 114         void fetchDescComplete();
 115         EventFunctionWrapper fetchCompleteEvent;
 116
 117         void fetchNextAddr(Addr address);
 118         void fetchAddrComplete();
 119         EventFunctionWrapper addrCompleteEvent;
 120
 121         void readCopyBytes();
 122         void readCopyBytesComplete();
 123         EventFunctionWrapper readCompleteEvent;
 124
 125         void writeCopyBytes();
 126         void writeCopyBytesComplete();
 127         EventFunctionWrapper writeCompleteEvent;
 128
 129         void writeCompletionStatus();
 130         void writeStatusComplete();
 131         EventFunctionWrapper statusCompleteEvent;
 132
 133
 134         void continueProcessing();
 135         void recvCommand();
 136         bool inDrain();
 137         void restartStateMachine();
 138     };
 139
 140   private:
 141
 142     Stats::Vector bytesCopied;
 143     Stats::Vector copiesProcessed;
 144
 145     // device registers
 146     CopyEngineReg::Regs regs;
 147
 148     // Array of channels each one with regs/dma port/etc
 149     std::vector<CopyEngineChannel*> chan;
 150
 151   public:
 152     typedef CopyEngineParams Params;
 153     const Params &
 154     params() const
 155     {
 156         return dynamic_cast<const Params &>(_params);
 157     }
 158     CopyEngine(const Params &params);
 159     ~CopyEngine();
 160
 161     void regStats() override;
 162
 163     Port &getPort(const std::string &if_name,
 164             PortID idx = InvalidPortID) override;
 165
 166     Tick read(PacketPtr pkt) override;
 167     Tick write(PacketPtr pkt) override;
 168
 169     void serialize(CheckpointOut &cp) const override;
 170     void unserialize(CheckpointIn &cp) override;
 171 };
 172
 173 #endif //__DEV_PCI_COPY_ENGINE_HH__
 174