src/dev/pci/copy_engine_defs.hh

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Register and structure descriptions for Intel's I/O AT DMA Engine
  33  */
  34 #include "base/bitfield.hh"
  35 #include "sim/serialize.hh"
  36
  37 namespace CopyEngineReg {
  38
  39
  40 // General Channel independant registers, 128 bytes starting at 0x00
  41 const uint32_t GEN_CHANCOUNT    = 0x00;
  42 const uint32_t GEN_XFERCAP      = 0x01;
  43 const uint32_t GEN_INTRCTRL     = 0x03;
  44 const uint32_t GEN_ATTNSTATUS   = 0x04;
  45
  46
  47 // Channel specific registers, each block is 128 bytes, starting at 0x80
  48 const uint32_t CHAN_CONTROL         = 0x00;
  49 const uint32_t CHAN_STATUS          = 0x04;
  50 const uint32_t CHAN_CHAINADDR       = 0x0C;
  51 const uint32_t CHAN_CHAINADDR_LOW   = 0x0C;
  52 const uint32_t CHAN_CHAINADDR_HIGH  = 0x10;
  53 const uint32_t CHAN_COMMAND         = 0x14;
  54 const uint32_t CHAN_CMPLNADDR       = 0x18;
  55 const uint32_t CHAN_CMPLNADDR_LOW   = 0x18;
  56 const uint32_t CHAN_CMPLNADDR_HIGH  = 0x1C;
  57 const uint32_t CHAN_ERROR           = 0x28;
  58
  59
  60 const uint32_t DESC_CTRL_INT_GEN    = 0x00000001;
  61 const uint32_t DESC_CTRL_SRC_SN     = 0x00000002;
  62 const uint32_t DESC_CTRL_DST_SN     = 0x00000004;
  63 const uint32_t DESC_CTRL_CP_STS     = 0x00000008;
  64 const uint32_t DESC_CTRL_FRAME      = 0x00000010;
  65 const uint32_t DESC_CTRL_NULL       = 0x00000020;
  66
  67 struct DmaDesc {
  68     uint32_t len;
  69     uint32_t command;
  70     Addr src;
  71     Addr dest;
  72     Addr next;
  73     uint64_t reserved1;
  74     uint64_t reserved2;
  75     uint64_t user1;
  76     uint64_t user2;
  77 };
  78
  79 #define ADD_FIELD8(NAME, OFFSET, BITS) \
  80     inline uint8_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
  81     inline void NAME(uint8_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
  82
  83 #define ADD_FIELD16(NAME, OFFSET, BITS) \
  84     inline uint16_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
  85     inline void NAME(uint16_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
  86
  87 #define ADD_FIELD32(NAME, OFFSET, BITS) \
  88     inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
  89     inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
  90
  91 #define ADD_FIELD64(NAME, OFFSET, BITS) \
  92     inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
  93     inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
  94
  95 template<class T>
  96 struct Reg {
  97     T _data;
  98     T operator()() { return _data; }
  99     const Reg<T> &operator=(T d) { _data = d; return *this;}
 100     bool operator==(T d) { return d == _data; }
 101     void operator()(T d) { _data = d; }
 102     Reg() { _data = 0; }
 103     void serialize(CheckpointOut &cp) const
 104     {
 105         SERIALIZE_SCALAR(_data);
 106     }
 107     void unserialize(CheckpointIn &cp)
 108     {
 109         UNSERIALIZE_SCALAR(_data);
 110     }
 111 };
 112
 113
 114 struct Regs : public Serializable {
 115     uint8_t chanCount;
 116     uint8_t xferCap;
 117
 118     struct INTRCTRL : public Reg<uint8_t> { // 0x03
 119         using Reg<uint8_t>::operator =;
 120         ADD_FIELD8(master_int_enable,0,1);
 121         ADD_FIELD8(interrupt_status,1,1);
 122         ADD_FIELD8(interrupt,2,1);
 123     };
 124     INTRCTRL intrctrl;
 125
 126     uint32_t attnStatus; // Read clears
 127
 128     void serialize(CheckpointOut &cp) const override
 129     {
 130         SERIALIZE_SCALAR(chanCount);
 131         SERIALIZE_SCALAR(xferCap);
 132         paramOut(cp, "intrctrl", intrctrl._data);
 133         SERIALIZE_SCALAR(attnStatus);
 134     }
 135
 136     void unserialize(CheckpointIn &cp) override
 137     {
 138         UNSERIALIZE_SCALAR(chanCount);
 139         UNSERIALIZE_SCALAR(xferCap);
 140         paramIn(cp, "intrctrl", intrctrl._data);
 141         UNSERIALIZE_SCALAR(attnStatus);
 142     }
 143
 144 };
 145
 146 struct ChanRegs : public Serializable {
 147     struct CHANCTRL : public Reg<uint16_t> { // channelX + 0x00
 148         using Reg<uint16_t>::operator =;
 149         ADD_FIELD16(interrupt_disable,0,1);
 150         ADD_FIELD16(error_completion_enable, 2,1);
 151         ADD_FIELD16(any_error_abort_enable,3,1);
 152         ADD_FIELD16(error_int_enable,4,1);
 153         ADD_FIELD16(desc_addr_snoop_control,5,1);
 154         ADD_FIELD16(in_use, 8,1);
 155     };
 156     CHANCTRL ctrl;
 157
 158     struct CHANSTS : public Reg<uint64_t> { // channelX + 0x04
 159         ADD_FIELD64(dma_transfer_status, 0, 3);
 160         ADD_FIELD64(unaffiliated_error, 3, 1);
 161         ADD_FIELD64(soft_error, 4, 1);
 162         ADD_FIELD64(compl_desc_addr, 6, 58);
 163     };
 164     CHANSTS status;
 165
 166     uint64_t descChainAddr;
 167
 168     struct CHANCMD : public Reg<uint8_t> { // channelX + 0x14
 169         ADD_FIELD8(start_dma,0,1);
 170         ADD_FIELD8(append_dma,1,1);
 171         ADD_FIELD8(suspend_dma,2,1);
 172         ADD_FIELD8(abort_dma,3,1);
 173         ADD_FIELD8(resume_dma,4,1);
 174         ADD_FIELD8(reset_dma,5,1);
 175     };
 176     CHANCMD command;
 177
 178     uint64_t completionAddr;
 179
 180     struct CHANERR : public Reg<uint32_t> { // channel X + 0x28
 181         ADD_FIELD32(source_addr_error,0,1);
 182         ADD_FIELD32(dest_addr_error,1,1);
 183         ADD_FIELD32(ndesc_addr_error,2,1);
 184         ADD_FIELD32(desc_error,3,1);
 185         ADD_FIELD32(chain_addr_error,4,1);
 186         ADD_FIELD32(chain_cmd_error,5,1);
 187         ADD_FIELD32(chipset_parity_error,6,1);
 188         ADD_FIELD32(dma_parity_error,7,1);
 189         ADD_FIELD32(read_data_error,8,1);
 190         ADD_FIELD32(write_data_error,9,1);
 191         ADD_FIELD32(desc_control_error,10,1);
 192         ADD_FIELD32(desc_len_error,11,1);
 193         ADD_FIELD32(completion_addr_error,12,1);
 194         ADD_FIELD32(interrupt_config_error,13,1);
 195         ADD_FIELD32(soft_error,14,1);
 196         ADD_FIELD32(unaffiliated_error,15,1);
 197     };
 198     CHANERR error;
 199
 200     void serialize(CheckpointOut &cp) const override
 201     {
 202         paramOut(cp, "ctrl", ctrl._data);
 203         paramOut(cp, "status", status._data);
 204         SERIALIZE_SCALAR(descChainAddr);
 205         paramOut(cp, "command", command._data);
 206         SERIALIZE_SCALAR(completionAddr);
 207         paramOut(cp, "error", error._data);
 208     }
 209
 210     void unserialize(CheckpointIn &cp) override
 211     {
 212         paramIn(cp, "ctrl", ctrl._data);
 213         paramIn(cp, "status", status._data);
 214         UNSERIALIZE_SCALAR(descChainAddr);
 215         paramIn(cp, "command", command._data);
 216         UNSERIALIZE_SCALAR(completionAddr);
 217         paramIn(cp, "error", error._data);
 218     }
 219
 220
 221 };
 222
 223 } // namespace CopyEngineReg
 224
 225