src/dev/pci/pcireg.h

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /* @file
  42  * Device register definitions for a device's PCI config space
  43  */
  44
  45 #ifndef __PCIREG_H__
  46 #define __PCIREG_H__
  47
  48 #include <sys/types.h>
  49
  50 #include "base/bitfield.hh"
  51 #include "base/bitunion.hh"
  52
  53 union PCIConfig {
  54     uint8_t data[64];
  55
  56     struct {
  57         uint16_t vendor;
  58         uint16_t device;
  59         uint16_t command;
  60         uint16_t status;
  61         uint8_t revision;
  62         uint8_t progIF;
  63         uint8_t subClassCode;
  64         uint8_t classCode;
  65         uint8_t cacheLineSize;
  66         uint8_t latencyTimer;
  67         uint8_t headerType;
  68         uint8_t bist;
  69         uint32_t baseAddr[6];
  70         uint32_t cardbusCIS;
  71         uint16_t subsystemVendorID;
  72         uint16_t subsystemID;
  73         uint32_t expansionROM;
  74         uint8_t capabilityPtr;
  75         // Was 8 bytes in the legacy PCI spec, but to support PCIe
  76         // this field is now 7 bytes with PCIe's addition of the
  77         // capability list pointer.
  78         uint8_t reserved[7];
  79         uint8_t interruptLine;
  80         uint8_t interruptPin;
  81         uint8_t minimumGrant;
  82         uint8_t maximumLatency;
  83     };
  84 };
  85
  86 // Common PCI offsets
  87 #define PCI_VENDOR_ID           0x00    // Vendor ID                    ro
  88 #define PCI_DEVICE_ID           0x02    // Device ID                    ro
  89 #define PCI_COMMAND             0x04    // Command                      rw
  90 #define PCI_STATUS              0x06    // Status                       rw
  91 #define PCI_REVISION_ID         0x08    // Revision ID                  ro
  92 #define PCI_CLASS_CODE          0x09    // Class Code                   ro
  93 #define PCI_SUB_CLASS_CODE      0x0A    // Sub Class Code               ro
  94 #define PCI_BASE_CLASS_CODE     0x0B    // Base Class Code              ro
  95 #define PCI_CACHE_LINE_SIZE     0x0C    // Cache Line Size              ro+
  96 #define PCI_LATENCY_TIMER       0x0D    // Latency Timer                ro+
  97 #define PCI_HEADER_TYPE         0x0E    // Header Type                  ro
  98 #define PCI_BIST                0x0F    // Built in self test           rw
  99
 100 // some pci command reg bitfields
 101 #define PCI_CMD_BME     0x04 // Bus master function enable
 102 #define PCI_CMD_MSE     0x02 // Memory Space Access enable
 103 #define PCI_CMD_IOSE    0x01 // I/O space enable
 104
 105 // Type 0 PCI offsets
 106 #define PCI0_BASE_ADDR0         0x10    // Base Address 0               rw
 107 #define PCI0_BASE_ADDR1         0x14    // Base Address 1               rw
 108 #define PCI0_BASE_ADDR2         0x18    // Base Address 2               rw
 109 #define PCI0_BASE_ADDR3         0x1C    // Base Address 3               rw
 110 #define PCI0_BASE_ADDR4         0x20    // Base Address 4               rw
 111 #define PCI0_BASE_ADDR5         0x24    // Base Address 5               rw
 112 #define PCI0_CIS                0x28    // CardBus CIS Pointer          ro
 113 #define PCI0_SUB_VENDOR_ID      0x2C    // Sub-Vendor ID                ro
 114 #define PCI0_SUB_SYSTEM_ID      0x2E    // Sub-System ID                ro
 115 #define PCI0_ROM_BASE_ADDR      0x30    // Expansion ROM Base Address   rw
 116 #define PCI0_CAP_PTR            0x34    // Capability list pointer      ro
 117 #define PCI0_RESERVED           0x35
 118 #define PCI0_INTERRUPT_LINE     0x3C    // Interrupt Line               rw
 119 #define PCI0_INTERRUPT_PIN      0x3D    // Interrupt Pin                ro
 120 #define PCI0_MINIMUM_GRANT      0x3E    // Maximum Grant                ro
 121 #define PCI0_MAXIMUM_LATENCY    0x3F    // Maximum Latency              ro
 122
 123 // Type 1 PCI offsets
 124 #define PCI1_BASE_ADDR0         0x10    // Base Address 0               rw
 125 #define PCI1_BASE_ADDR1         0x14    // Base Address 1               rw
 126 #define PCI1_PRI_BUS_NUM        0x18    // Primary Bus Number           rw
 127 #define PCI1_SEC_BUS_NUM        0x19    // Secondary Bus Number         rw
 128 #define PCI1_SUB_BUS_NUM        0x1A    // Subordinate Bus Number       rw
 129 #define PCI1_SEC_LAT_TIMER      0x1B    // Secondary Latency Timer      ro+
 130 #define PCI1_IO_BASE            0x1C    // I/O Base                     rw
 131 #define PCI1_IO_LIMIT           0x1D    // I/O Limit                    rw
 132 #define PCI1_SECONDARY_STATUS   0x1E    // Secondary Status             rw
 133 #define PCI1_MEM_BASE           0x20    // Memory Base                  rw
 134 #define PCI1_MEM_LIMIT          0x22    // Memory Limit                 rw
 135 #define PCI1_PRF_MEM_BASE       0x24    // Prefetchable Memory Base     rw
 136 #define PCI1_PRF_MEM_LIMIT      0x26    // Prefetchable Memory Limit    rw
 137 #define PCI1_PRF_BASE_UPPER     0x28    // Prefetchable Base Upper 32   rw
 138 #define PCI1_PRF_LIMIT_UPPER    0x2C    // Prefetchable Limit Upper 32  rw
 139 #define PCI1_IO_BASE_UPPER      0x30    // I/O Base Upper 16 bits       rw
 140 #define PCI1_IO_LIMIT_UPPER     0x32    // I/O Limit Upper 16 bits      rw
 141 #define PCI1_RESERVED           0x34    // Reserved                     ro
 142 #define PCI1_ROM_BASE_ADDR      0x38    // Expansion ROM Base Address   rw
 143 #define PCI1_INTR_LINE          0x3C    // Interrupt Line               rw
 144 #define PCI1_INTR_PIN           0x3D    // Interrupt Pin                ro
 145 #define PCI1_BRIDGE_CTRL        0x3E    // Bridge Control               rw
 146
 147 // Device specific offsets
 148 #define PCI_DEVICE_SPECIFIC             0x40    // 192 bytes
 149 #define PCI_CONFIG_SIZE         0xFF
 150
 151 // Some Vendor IDs
 152 #define PCI_VENDOR_DEC                  0x1011
 153 #define PCI_VENDOR_NCR                  0x101A
 154 #define PCI_VENDOR_QLOGIC               0x1077
 155 #define PCI_VENDOR_SIMOS                0x1291
 156
 157 // Some Product IDs
 158 #define PCI_PRODUCT_DEC_PZA             0x0008
 159 #define PCI_PRODUCT_NCR_810             0x0001
 160 #define PCI_PRODUCT_QLOGIC_ISP1020      0x1020
 161 #define PCI_PRODUCT_SIMOS_SIMOS         0x1291
 162 #define PCI_PRODUCT_SIMOS_ETHER         0x1292
 163
 164 /**
 165  * PCIe capability list offsets internal to the entry.
 166  * Actual offsets in the PCI config space are defined in
 167  * the python files setting up the system.
 168  */
 169 #define PMCAP_ID 0x00
 170 #define PMCAP_PC 0x02
 171 #define PMCAP_PMCS 0x04
 172 #define PMCAP_SIZE 0x06
 173
 174 #define MSICAP_ID 0x00
 175 #define MSICAP_MC 0x02
 176 #define MSICAP_MA 0x04
 177 #define MSICAP_MUA 0x08
 178 #define MSICAP_MD 0x0C
 179 #define MSICAP_MMASK 0x10
 180 #define MSICAP_MPEND 0x14
 181 #define MSICAP_SIZE 0x18
 182
 183 #define MSIXCAP_ID 0x00
 184 #define MSIXCAP_MXC 0x02
 185 #define MSIXCAP_MTAB 0x04
 186 #define MSIXCAP_MPBA 0x08
 187 #define MSIXCAP_SIZE 0x0C
 188
 189 #define PXCAP_ID 0x00
 190 #define PXCAP_PXCAP 0x02
 191 #define PXCAP_PXDCAP 0x04
 192 #define PXCAP_PXDC 0x08
 193 #define PXCAP_PXDS 0x0A
 194 #define PXCAP_PXLCAP 0x0C
 195 #define PXCAP_PXLC 0x10
 196 #define PXCAP_PXLS 0x12
 197 #define PXCAP_PXDCAP2 0x24
 198 #define PXCAP_PXDC2 0x28
 199 #define PXCAP_SIZE 0x30
 200
 201 /** @struct PMCAP
 202  *  Defines the Power Management capability register and all its associated
 203  *  bitfields for a PCIe device.
 204  */
 205 union PMCAP {
 206     uint8_t data[6];
 207     struct {
 208         uint16_t pid;  /* 0:7  cid
 209                         * 8:15 next
 210                         */
 211         uint16_t pc;   /* 0:2   vs
 212                         * 3     pmec
 213                         * 4     reserved
 214                         * 5     dsi
 215                         * 6:8   auxc
 216                         * 9     d1s
 217                         * 10    d2s
 218                         * 11:15 psup
 219                         */
 220         uint16_t pmcs; /* 0:1   ps
 221                         * 2     reserved
 222                         * 3     nsfrst
 223                         * 4:7   reserved
 224                         * 8     pmee
 225                         * 9:12  dse
 226                         * 13:14 dsc
 227                         * 15    pmes
 228                         */
 229     };
 230 };
 231
 232 /** @struct MSICAP
 233  *  Defines the MSI Capability register and its associated bitfields for
 234  *  the a PCI/PCIe device.  Both the MSI capability and the MSIX capability
 235  *  can be filled in if a device model supports both, but only 1 of
 236  *  MSI/MSIX/INTx interrupt mode can be selected at a given time.
 237  */
 238 union MSICAP {
 239     uint8_t data[24];
 240     struct {
 241         uint16_t mid;  /* 0:7  cid
 242                         *  8:15 next
 243                         */
 244         uint16_t mc;   /* 0     msie;
 245                         * 1:3   mmc;
 246                         * 4:6   mme;
 247                         * 7     c64;
 248                         * 8     pvm;
 249                         * 9:15  reserved;
 250                         */
 251         uint32_t ma;   /* 0:1  reserved
 252                         * 2:31 addr
 253                         */
 254         uint32_t mua;
 255         uint16_t md;
 256         uint32_t mmask;
 257         uint32_t mpend;
 258    };
 259 };
 260
 261 /** @struct MSIX
 262  *  Defines the MSI-X Capability register and its associated bitfields for
 263  *  a PCIe device.
 264  */
 265 union MSIXCAP {
 266     uint8_t data[12];
 267     struct {
 268         uint16_t mxid; /* 0:7  cid
 269                         *  8:15 next
 270                         */
 271         uint16_t mxc;  /* 0:10  ts;
 272                         * 11:13 reserved;
 273                         * 14    fm;
 274                         * 15    mxe;
 275                         */
 276         uint32_t mtab; /* 0:2   tbir;
 277                         * 3:31  to;
 278                         */
 279         uint32_t mpba; /* 0:2   pbir;
 280                         * 3:31>  pbao;
 281                         */
 282     };
 283 };
 284
 285 union MSIXTable {
 286     struct {
 287         uint32_t addr_lo;
 288         uint32_t addr_hi;
 289         uint32_t msg_data;
 290         uint32_t vec_ctrl;
 291     } fields;
 292     uint32_t data[4];
 293 };
 294
 295 #define MSIXVECS_PER_PBA 64
 296 struct MSIXPbaEntry {
 297     uint64_t bits;
 298 };
 299
 300 /** @struct PXCAP
 301  *  Defines the PCI Express capability register and its associated bitfields
 302  *  for a PCIe device.
 303  */
 304 struct PXCAP {
 305     uint8_t data[48];
 306     struct {
 307         uint16_t pxid; /* 0:7  cid
 308                         *  8:15 next
 309                         */
 310         uint16_t pxcap; /* 0:3   ver;
 311                          * 4:7   dpt;
 312                          * 8     si;
 313                          * 9:13  imn;
 314                          * 14:15 reserved;
 315                          */
 316         uint32_t pxdcap; /* 0:2   mps;
 317                           * 3:4   pfs;
 318                           * 5     etfs;
 319                           * 6:8   l0sl;
 320                           * 9:11  l1l;
 321                           * 12:14 reserved;
 322                           * 15    rer;
 323                           * 16:17 reserved;
 324                           * 18:25 csplv;
 325                           * 26:27 cspls;
 326                           * 28    flrc;
 327                           * 29:31 reserved;
 328                           */
 329         uint16_t pxdc; /* 0     cere;
 330                         * 1     nfere;
 331                         * 2     fere;
 332                         * 3     urre;
 333                         * 4     ero;
 334                         * 5:7   mps;
 335                         * 8     ete;
 336                         * 9     pfe;
 337                         * 10    appme;
 338                         * 11    ens;
 339                         * 12:14 mrrs;
 340                         * 15    func_reset;
 341                         */
 342         uint16_t pxds; /* 0     ced;
 343                         * 1     nfed;
 344                         * 2     fed;
 345                         * 3     urd;
 346                         * 4     apd;
 347                         * 5     tp;
 348                         * 6:15  reserved;
 349                         */
 350         uint32_t pxlcap; /* 0:3   sls;
 351                           * 4:9   mlw;
 352                           * 10:11 aspms;
 353                           * 12:14 l0sel;
 354                           * 15:17 l1el;
 355                           * 18    cpm;
 356                           * 19    sderc;
 357                           * 20    dllla;
 358                           * 21    lbnc;
 359                           * 22:23 reserved;
 360                           * 24:31 pn;
 361                           */
 362         uint16_t pxlc; /* 0:1   aspmc;
 363                         * 2     reserved;
 364                         * 3     rcb;
 365                         * 4:5   reserved;
 366                         * 6     ccc;
 367                         * 7     es;
 368                         * 8     ecpm;
 369                         * 9     hawd;
 370                         * 10:15 reserved;
 371                         */
 372         uint16_t pxls; /* 0:3   cls;
 373                         * 4:9   nlw;
 374                         * 10:11 reserved;
 375                         * 12    slot_clk_config;
 376                         * 13:15 reserved;
 377                         */
 378         uint8_t reserved[20];
 379         uint32_t pxdcap2; /* 0:3   ctrs;
 380                            * 4     ctds;
 381                            * 5     arifs;
 382                            * 6     aors;
 383                            * 7     aocs32;
 384                            * 8     aocs64;
 385                            * 9     ccs128;
 386                            * 10    nprpr;
 387                            * 11    ltrs;
 388                            * 12:13 tphcs;
 389                            * 14:17 reserved;
 390                            * 18:19 obffs;
 391                            * 20    effs;
 392                            * 21    eetps;
 393                            * 22:23 meetp;
 394                            * 24:31 reserved;
 395                            */
 396         uint32_t pxdc2; /* 0:3   ctv;
 397                          * 4     ctd;
 398                          * 5:9   reserved;
 399                          * 10    ltrme;
 400                          * 11:12 reserved;
 401                          * 13:14 obffe;
 402                          * 15:31 reserved;
 403                          */
 404     };
 405 };
 406 #endif // __PCIREG_H__