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34 * A single PCI device configuration space entry.
41 #include "base/inifile.hh"
42 #include "base/intmath.hh"
43 #include "base/misc.hh"
44 #include "base/str.hh"
45 #include "base/trace.hh"
46 #include "debug/PCIDEV.hh"
47 #include "dev/alpha/tsunamireg.h"
48 #include "dev/pciconfigall.hh"
49 #include "dev/pcidev.hh"
50 #include "mem/packet.hh"
51 #include "mem/packet_access.hh"
52 #include "sim/byteswap.hh"
53 #include "sim/core.hh"
56 PciDev::PciConfigPort::PciConfigPort(PciDev
*dev
, int busid
, int devid
,
57 int funcid
, Platform
*p
)
58 : SimpleTimingPort(dev
->name() + "-pciconf", dev
), device(dev
),
59 platform(p
), busId(busid
), deviceId(devid
), functionId(funcid
)
61 configAddr
= platform
->calcPciConfigAddr(busId
, deviceId
, functionId
);
66 PciDev::PciConfigPort::recvAtomic(PacketPtr pkt
)
68 assert(pkt
->getAddr() >= configAddr
&&
69 pkt
->getAddr() < configAddr
+ PCI_CONFIG_SIZE
);
70 return pkt
->isRead() ? device
->readConfig(pkt
) : device
->writeConfig(pkt
);
74 PciDev::PciConfigPort::getAddrRanges() const
77 if (configAddr
!= ULL(-1))
78 ranges
.push_back(RangeSize(configAddr
, PCI_CONFIG_SIZE
+1));
83 PciDev::PciDev(const Params
*p
)
84 : DmaDevice(p
), platform(p
->platform
), pioDelay(p
->pio_latency
),
85 configDelay(p
->config_latency
),
86 configPort(this, params()->pci_bus
, params()->pci_dev
,
87 params()->pci_func
, params()->platform
)
89 config
.vendor
= htole(p
->VendorID
);
90 config
.device
= htole(p
->DeviceID
);
91 config
.command
= htole(p
->Command
);
92 config
.status
= htole(p
->Status
);
93 config
.revision
= htole(p
->Revision
);
94 config
.progIF
= htole(p
->ProgIF
);
95 config
.subClassCode
= htole(p
->SubClassCode
);
96 config
.classCode
= htole(p
->ClassCode
);
97 config
.cacheLineSize
= htole(p
->CacheLineSize
);
98 config
.latencyTimer
= htole(p
->LatencyTimer
);
99 config
.headerType
= htole(p
->HeaderType
);
100 config
.bist
= htole(p
->BIST
);
102 config
.baseAddr
[0] = htole(p
->BAR0
);
103 config
.baseAddr
[1] = htole(p
->BAR1
);
104 config
.baseAddr
[2] = htole(p
->BAR2
);
105 config
.baseAddr
[3] = htole(p
->BAR3
);
106 config
.baseAddr
[4] = htole(p
->BAR4
);
107 config
.baseAddr
[5] = htole(p
->BAR5
);
108 config
.cardbusCIS
= htole(p
->CardbusCIS
);
109 config
.subsystemVendorID
= htole(p
->SubsystemVendorID
);
110 config
.subsystemID
= htole(p
->SubsystemID
);
111 config
.expansionROM
= htole(p
->ExpansionROM
);
112 config
.reserved0
= 0;
113 config
.reserved1
= 0;
114 config
.interruptLine
= htole(p
->InterruptLine
);
115 config
.interruptPin
= htole(p
->InterruptPin
);
116 config
.minimumGrant
= htole(p
->MinimumGrant
);
117 config
.maximumLatency
= htole(p
->MaximumLatency
);
119 BARSize
[0] = p
->BAR0Size
;
120 BARSize
[1] = p
->BAR1Size
;
121 BARSize
[2] = p
->BAR2Size
;
122 BARSize
[3] = p
->BAR3Size
;
123 BARSize
[4] = p
->BAR4Size
;
124 BARSize
[5] = p
->BAR5Size
;
126 legacyIO
[0] = p
->BAR0LegacyIO
;
127 legacyIO
[1] = p
->BAR1LegacyIO
;
128 legacyIO
[2] = p
->BAR2LegacyIO
;
129 legacyIO
[3] = p
->BAR3LegacyIO
;
130 legacyIO
[4] = p
->BAR4LegacyIO
;
131 legacyIO
[5] = p
->BAR5LegacyIO
;
133 for (int i
= 0; i
< 6; ++i
) {
135 BARAddrs
[i
] = platform
->calcPciIOAddr(letoh(config
.baseAddr
[i
]));
136 config
.baseAddr
[i
] = 0;
139 uint32_t barsize
= BARSize
[i
];
140 if (barsize
!= 0 && !isPowerOf2(barsize
)) {
141 fatal("BAR %d size %d is not a power of 2\n", i
, BARSize
[i
]);
146 platform
->registerPciDevice(p
->pci_bus
, p
->pci_dev
, p
->pci_func
,
147 letoh(config
.interruptLine
));
153 if (!configPort
.isConnected())
154 panic("PCI config port on %s not connected to anything!\n", name());
155 configPort
.sendRangeChange();
160 PciDev::drain(DrainManager
*dm
)
163 count
= pioPort
.drain(dm
) + dmaPort
.drain(dm
) + configPort
.drain(dm
);
165 setDrainState(Drainable::Draining
);
167 setDrainState(Drainable::Drained
);
172 PciDev::readConfig(PacketPtr pkt
)
174 int offset
= pkt
->getAddr() & PCI_CONFIG_SIZE
;
175 if (offset
>= PCI_DEVICE_SPECIFIC
)
176 panic("Device specific PCI config space not implemented!\n");
180 switch (pkt
->getSize()) {
181 case sizeof(uint8_t):
182 pkt
->set
<uint8_t>(config
.data
[offset
]);
184 "readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
185 params()->pci_dev
, params()->pci_func
, offset
,
186 (uint32_t)pkt
->get
<uint8_t>());
188 case sizeof(uint16_t):
189 pkt
->set
<uint16_t>(*(uint16_t*)&config
.data
[offset
]);
191 "readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
192 params()->pci_dev
, params()->pci_func
, offset
,
193 (uint32_t)pkt
->get
<uint16_t>());
195 case sizeof(uint32_t):
196 pkt
->set
<uint32_t>(*(uint32_t*)&config
.data
[offset
]);
198 "readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
199 params()->pci_dev
, params()->pci_func
, offset
,
200 (uint32_t)pkt
->get
<uint32_t>());
203 panic("invalid access size(?) for PCI configspace!\n");
205 pkt
->makeAtomicResponse();
211 PciDev::getAddrRanges() const
213 AddrRangeList ranges
;
215 for (x
= 0; x
< 6; x
++)
216 if (BARAddrs
[x
] != 0)
217 ranges
.push_back(RangeSize(BARAddrs
[x
],BARSize
[x
]));
222 PciDev::writeConfig(PacketPtr pkt
)
224 int offset
= pkt
->getAddr() & PCI_CONFIG_SIZE
;
225 if (offset
>= PCI_DEVICE_SPECIFIC
)
226 panic("Device specific PCI config space not implemented!\n");
228 switch (pkt
->getSize()) {
229 case sizeof(uint8_t):
231 case PCI0_INTERRUPT_LINE
:
232 config
.interruptLine
= pkt
->get
<uint8_t>();
234 case PCI_CACHE_LINE_SIZE
:
235 config
.cacheLineSize
= pkt
->get
<uint8_t>();
237 case PCI_LATENCY_TIMER
:
238 config
.latencyTimer
= pkt
->get
<uint8_t>();
240 /* Do nothing for these read-only registers */
241 case PCI0_INTERRUPT_PIN
:
242 case PCI0_MINIMUM_GRANT
:
243 case PCI0_MAXIMUM_LATENCY
:
245 case PCI_REVISION_ID
:
248 panic("writing to a read only register");
251 "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
252 params()->pci_dev
, params()->pci_func
, offset
,
253 (uint32_t)pkt
->get
<uint8_t>());
255 case sizeof(uint16_t):
258 config
.command
= pkt
->get
<uint8_t>();
261 config
.status
= pkt
->get
<uint8_t>();
263 case PCI_CACHE_LINE_SIZE
:
264 config
.cacheLineSize
= pkt
->get
<uint8_t>();
267 panic("writing to a read only register");
270 "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
271 params()->pci_dev
, params()->pci_func
, offset
,
272 (uint32_t)pkt
->get
<uint16_t>());
274 case sizeof(uint32_t):
276 case PCI0_BASE_ADDR0
:
277 case PCI0_BASE_ADDR1
:
278 case PCI0_BASE_ADDR2
:
279 case PCI0_BASE_ADDR3
:
280 case PCI0_BASE_ADDR4
:
281 case PCI0_BASE_ADDR5
:
283 int barnum
= BAR_NUMBER(offset
);
285 if (!legacyIO
[barnum
]) {
286 // convert BAR values to host endianness
287 uint32_t he_old_bar
= letoh(config
.baseAddr
[barnum
]);
288 uint32_t he_new_bar
= letoh(pkt
->get
<uint32_t>());
291 BAR_IO_SPACE(he_old_bar
) ? BAR_IO_MASK
: BAR_MEM_MASK
;
293 // Writing 0xffffffff to a BAR tells the card to set the
294 // value of the bar to a bitmask indicating the size of
296 if (he_new_bar
== 0xffffffff) {
297 he_new_bar
= ~(BARSize
[barnum
] - 1);
299 // does it mean something special to write 0 to a BAR?
300 he_new_bar
&= ~bar_mask
;
302 BARAddrs
[barnum
] = BAR_IO_SPACE(he_old_bar
) ?
303 platform
->calcPciIOAddr(he_new_bar
) :
304 platform
->calcPciMemAddr(he_new_bar
);
305 pioPort
.sendRangeChange();
308 config
.baseAddr
[barnum
] = htole((he_new_bar
& ~bar_mask
) |
309 (he_old_bar
& bar_mask
));
314 case PCI0_ROM_BASE_ADDR
:
315 if (letoh(pkt
->get
<uint32_t>()) == 0xfffffffe)
316 config
.expansionROM
= htole((uint32_t)0xffffffff);
318 config
.expansionROM
= pkt
->get
<uint32_t>();
322 // This could also clear some of the error bits in the Status
323 // register. However they should never get set, so lets ignore
325 config
.command
= pkt
->get
<uint32_t>();
329 DPRINTF(PCIDEV
, "Writing to a read only register");
332 "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
333 params()->pci_dev
, params()->pci_func
, offset
,
334 (uint32_t)pkt
->get
<uint32_t>());
337 panic("invalid access size(?) for PCI configspace!\n");
339 pkt
->makeAtomicResponse();
344 PciDev::serialize(std::ostream
&os
)
346 SERIALIZE_ARRAY(BARSize
, sizeof(BARSize
) / sizeof(BARSize
[0]));
347 SERIALIZE_ARRAY(BARAddrs
, sizeof(BARAddrs
) / sizeof(BARAddrs
[0]));
348 SERIALIZE_ARRAY(config
.data
, sizeof(config
.data
) / sizeof(config
.data
[0]));
352 PciDev::unserialize(Checkpoint
*cp
, const std::string
§ion
)
354 UNSERIALIZE_ARRAY(BARSize
, sizeof(BARSize
) / sizeof(BARSize
[0]));
355 UNSERIALIZE_ARRAY(BARAddrs
, sizeof(BARAddrs
) / sizeof(BARAddrs
[0]));
356 UNSERIALIZE_ARRAY(config
.data
,
357 sizeof(config
.data
) / sizeof(config
.data
[0]));
358 pioPort
.sendRangeChange();