src/dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  *          Andrew Schultz
  30  *          Miguel Serrano
  31  */
  32
  33 /* @file
  34  * A single PCI device configuration space entry.
  35  */
  36
  37 #include <list>
  38 #include <string>
  39 #include <vector>
  40
  41 #include "base/inifile.hh"
  42 #include "base/misc.hh"
  43 #include "base/str.hh"  // for to_number
  44 #include "base/trace.hh"
  45 #include "dev/pciconfigall.hh"
  46 #include "dev/pcidev.hh"
  47 #include "dev/tsunamireg.h"
  48 #include "mem/packet.hh"
  49 #include "sim/builder.hh"
  50 #include "sim/byteswap.hh"
  51 #include "sim/param.hh"
  52 #include "sim/root.hh"
  53
  54 using namespace std;
  55
  56 PciDev::PciDev(Params *p)
  57     : DmaDevice(p), plat(p->platform), configData(p->configData),
  58       pioDelay(p->pio_delay)
  59 {
  60     // copy the config data from the PciConfigData object
  61     if (configData) {
  62         memcpy(config.data, configData->config.data, sizeof(config.data));
  63         memcpy(BARSize, configData->BARSize, sizeof(BARSize));
  64         memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
  65     } else
  66         panic("NULL pointer to configuration data");
  67
  68     // Setup pointer in config space to point to this entry
  69     if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
  70         panic("Two PCI devices occuping same dev: %#x func: %#x",
  71               p->deviceNum, p->functionNum);
  72     else
  73         p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
  74 }
  75
  76 void
  77 PciDev::readConfig(int offset, uint8_t *data)
  78 {
  79     if (offset >= PCI_DEVICE_SPECIFIC)
  80         panic("Device specific PCI config space not implemented!\n");
  81
  82     *data = config.data[offset];
  83
  84     DPRINTF(PCIDEV,
  85             "read device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
  86             params()->deviceNum, params()->functionNum, offset, *data);
  87 }
  88
  89 void
  90 PciDev::addressRanges(AddrRangeList &range_list)
  91 {
  92     int x = 0;
  93     range_list.clear();
  94     for (x = 0; x < 6; x++)
  95         if (BARAddrs[x] != 0)
  96             range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
  97 }
  98
  99 void
 100 PciDev::readConfig(int offset, uint16_t *data)
 101 {
 102     if (offset >= PCI_DEVICE_SPECIFIC)
 103         panic("Device specific PCI config space not implemented!\n");
 104
 105     *data = *(uint16_t*)&config.data[offset];
 106
 107     DPRINTF(PCIDEV,
 108             "read device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
 109             params()->deviceNum, params()->functionNum, offset, *data);
 110 }
 111
 112 void
 113 PciDev::readConfig(int offset, uint32_t *data)
 114 {
 115     if (offset >= PCI_DEVICE_SPECIFIC)
 116         panic("Device specific PCI config space not implemented!\n");
 117
 118     *data = *(uint32_t*)&config.data[offset];
 119
 120     DPRINTF(PCIDEV,
 121             "read device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
 122             params()->deviceNum, params()->functionNum, offset, *data);
 123 }
 124
 125
 126 void
 127 PciDev::writeConfig(int offset,  const uint8_t data)
 128 {
 129     if (offset >= PCI_DEVICE_SPECIFIC)
 130         panic("Device specific PCI config space not implemented!\n");
 131
 132     DPRINTF(PCIDEV,
 133             "write device: %#x function: %#x reg: %#x size: 1 data: %#x\n",
 134             params()->deviceNum, params()->functionNum, offset, data);
 135
 136     switch (offset) {
 137       case PCI0_INTERRUPT_LINE:
 138         config.interruptLine = data;
 139       case PCI_CACHE_LINE_SIZE:
 140         config.cacheLineSize = data;
 141       case PCI_LATENCY_TIMER:
 142         config.latencyTimer = data;
 143         break;
 144       /* Do nothing for these read-only registers */
 145       case PCI0_INTERRUPT_PIN:
 146       case PCI0_MINIMUM_GRANT:
 147       case PCI0_MAXIMUM_LATENCY:
 148       case PCI_CLASS_CODE:
 149       case PCI_REVISION_ID:
 150         break;
 151       default:
 152         panic("writing to a read only register");
 153     }
 154 }
 155
 156 void
 157 PciDev::writeConfig(int offset, const uint16_t data)
 158 {
 159     if (offset >= PCI_DEVICE_SPECIFIC)
 160         panic("Device specific PCI config space not implemented!\n");
 161
 162     DPRINTF(PCIDEV,
 163             "write device: %#x function: %#x reg: %#x size: 2 data: %#x\n",
 164             params()->deviceNum, params()->functionNum, offset, data);
 165
 166     switch (offset) {
 167       case PCI_COMMAND:
 168         config.command = data;
 169       case PCI_STATUS:
 170         config.status = data;
 171       case PCI_CACHE_LINE_SIZE:
 172         config.cacheLineSize = data;
 173         break;
 174       default:
 175         panic("writing to a read only register");
 176     }
 177 }
 178
 179
 180 void
 181 PciDev::writeConfig(int offset, const uint32_t data)
 182 {
 183     if (offset >= PCI_DEVICE_SPECIFIC)
 184         panic("Device specific PCI config space not implemented!\n");
 185
 186     DPRINTF(PCIDEV,
 187             "write device: %#x function: %#x reg: %#x size: 4 data: %#x\n",
 188             params()->deviceNum, params()->functionNum, offset, data);
 189
 190     switch (offset) {
 191       case PCI0_BASE_ADDR0:
 192       case PCI0_BASE_ADDR1:
 193       case PCI0_BASE_ADDR2:
 194       case PCI0_BASE_ADDR3:
 195       case PCI0_BASE_ADDR4:
 196       case PCI0_BASE_ADDR5:
 197
 198         uint32_t barnum, bar_mask;
 199         Addr base_addr, base_size, space_base;
 200
 201         barnum = BAR_NUMBER(offset);
 202
 203         if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
 204             bar_mask = BAR_IO_MASK;
 205             space_base = TSUNAMI_PCI0_IO;
 206         } else {
 207             bar_mask = BAR_MEM_MASK;
 208             space_base = TSUNAMI_PCI0_MEMORY;
 209         }
 210
 211         // Writing 0xffffffff to a BAR tells the card to set the
 212         // value of the bar to size of memory it needs
 213         if (letoh(data) == 0xffffffff) {
 214             // This is I/O Space, bottom two bits are read only
 215
 216             config.baseAddr[barnum] = letoh(
 217                     (~(BARSize[barnum] - 1) & ~bar_mask) |
 218                     (letoh(config.baseAddr[barnum]) & bar_mask));
 219         } else {
 220             config.baseAddr[barnum] = letoh(
 221                 (letoh(data) & ~bar_mask) |
 222                 (letoh(config.baseAddr[barnum]) & bar_mask));
 223
 224             if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
 225                 base_addr = (letoh(data) & ~bar_mask) + space_base;
 226                 base_size = BARSize[barnum];
 227                 BARAddrs[barnum] = base_addr;
 228
 229             pioPort->sendStatusChange(Port::RangeChange);
 230             }
 231         }
 232         break;
 233
 234       case PCI0_ROM_BASE_ADDR:
 235         if (letoh(data) == 0xfffffffe)
 236             config.expansionROM = htole((uint32_t)0xffffffff);
 237         else
 238             config.expansionROM = data;
 239         break;
 240
 241       case PCI_COMMAND:
 242         // This could also clear some of the error bits in the Status
 243         // register. However they should never get set, so lets ignore
 244         // it for now
 245         config.command = data;
 246         break;
 247
 248       default:
 249         DPRINTF(PCIDEV, "Writing to a read only register");
 250     }
 251 }
 252
 253 void
 254 PciDev::serialize(ostream &os)
 255 {
 256     SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
 257     SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
 258     SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
 259 }
 260
 261 void
 262 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 263 {
 264     UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
 265     UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
 266     UNSERIALIZE_ARRAY(config.data,
 267                       sizeof(config.data) / sizeof(config.data[0]));
 268 }
 269
 270 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 271
 272 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 273
 274     Param<uint16_t> VendorID;
 275     Param<uint16_t> DeviceID;
 276     Param<uint16_t> Command;
 277     Param<uint16_t> Status;
 278     Param<uint8_t> Revision;
 279     Param<uint8_t> ProgIF;
 280     Param<uint8_t> SubClassCode;
 281     Param<uint8_t> ClassCode;
 282     Param<uint8_t> CacheLineSize;
 283     Param<uint8_t> LatencyTimer;
 284     Param<uint8_t> HeaderType;
 285     Param<uint8_t> BIST;
 286     Param<uint32_t> BAR0;
 287     Param<uint32_t> BAR1;
 288     Param<uint32_t> BAR2;
 289     Param<uint32_t> BAR3;
 290     Param<uint32_t> BAR4;
 291     Param<uint32_t> BAR5;
 292     Param<uint32_t> CardbusCIS;
 293     Param<uint16_t> SubsystemVendorID;
 294     Param<uint16_t> SubsystemID;
 295     Param<uint32_t> ExpansionROM;
 296     Param<uint8_t> InterruptLine;
 297     Param<uint8_t> InterruptPin;
 298     Param<uint8_t> MinimumGrant;
 299     Param<uint8_t> MaximumLatency;
 300     Param<uint32_t> BAR0Size;
 301     Param<uint32_t> BAR1Size;
 302     Param<uint32_t> BAR2Size;
 303     Param<uint32_t> BAR3Size;
 304     Param<uint32_t> BAR4Size;
 305     Param<uint32_t> BAR5Size;
 306
 307 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 308
 309 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 310
 311     INIT_PARAM(VendorID, "Vendor ID"),
 312     INIT_PARAM(DeviceID, "Device ID"),
 313     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 314     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 315     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 316     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 317     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 318     INIT_PARAM(ClassCode, "Class Code"),
 319     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 320     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 321     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 322     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 323     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 324     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 325     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 326     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 327     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 328     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 329     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 330     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 331     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 332     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 333     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 334     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 335     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 336     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 337     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 338     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 339     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 340     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 341     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 342     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 343
 344 END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 345
 346 CREATE_SIM_OBJECT(PciConfigData)
 347 {
 348     PciConfigData *data = new PciConfigData(getInstanceName());
 349
 350     data->config.vendor = htole(VendorID);
 351     data->config.device = htole(DeviceID);
 352     data->config.command = htole(Command);
 353     data->config.status = htole(Status);
 354     data->config.revision = htole(Revision);
 355     data->config.progIF = htole(ProgIF);
 356     data->config.subClassCode = htole(SubClassCode);
 357     data->config.classCode = htole(ClassCode);
 358     data->config.cacheLineSize = htole(CacheLineSize);
 359     data->config.latencyTimer = htole(LatencyTimer);
 360     data->config.headerType = htole(HeaderType);
 361     data->config.bist = htole(BIST);
 362
 363     data->config.baseAddr0 = htole(BAR0);
 364     data->config.baseAddr1 = htole(BAR1);
 365     data->config.baseAddr2 = htole(BAR2);
 366     data->config.baseAddr3 = htole(BAR3);
 367     data->config.baseAddr4 = htole(BAR4);
 368     data->config.baseAddr5 = htole(BAR5);
 369     data->config.cardbusCIS = htole(CardbusCIS);
 370     data->config.subsystemVendorID = htole(SubsystemVendorID);
 371     data->config.subsystemID = htole(SubsystemVendorID);
 372     data->config.expansionROM = htole(ExpansionROM);
 373     data->config.interruptLine = htole(InterruptLine);
 374     data->config.interruptPin = htole(InterruptPin);
 375     data->config.minimumGrant = htole(MinimumGrant);
 376     data->config.maximumLatency = htole(MaximumLatency);
 377
 378     data->BARSize[0] = BAR0Size;
 379     data->BARSize[1] = BAR1Size;
 380     data->BARSize[2] = BAR2Size;
 381     data->BARSize[3] = BAR3Size;
 382     data->BARSize[4] = BAR4Size;
 383     data->BARSize[5] = BAR5Size;
 384
 385     return data;
 386 }
 387
 388 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
 389
 390 #endif // DOXYGEN_SHOULD_SKIP_THIS