src/dev/pcidev.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  *          Andrew Schultz
  30  *          Nathan Binkert
  31  */
  32
  33 /* @file
  34  * Interface for devices using PCI configuration
  35  */
  36
  37 #ifndef __DEV_PCIDEV_HH__
  38 #define __DEV_PCIDEV_HH__
  39
  40 #include <cstring>
  41
  42 #include "dev/io_device.hh"
  43 #include "dev/pcireg.h"
  44 #include "dev/platform.hh"
  45 #include "sim/byteswap.hh"
  46
  47 #define BAR_IO_MASK 0x3
  48 #define BAR_MEM_MASK 0xF
  49 #define BAR_IO_SPACE_BIT 0x1
  50 #define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
  51 #define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
  52
  53
  54 /**
  55  * This class encapulates the first 64 bytes of a singles PCI
  56  * devices config space that in configured by the configuration file.
  57  */
  58 class PciConfigData : public SimObject
  59 {
  60   public:
  61     /**
  62      * Constructor to initialize the devices config space to 0.
  63      */
  64     PciConfigData(const std::string &name)
  65         : SimObject(name)
  66     {
  67         std::memset(config.data, 0, sizeof(config.data));
  68         std::memset(BARSize, 0, sizeof(BARSize));
  69     }
  70
  71     /** The first 64 bytes */
  72     PCIConfig config;
  73
  74     /** The size of the BARs */
  75     uint32_t BARSize[6];
  76 };
  77
  78
  79 /**
  80  * PCI device, base implementation is only config space.
  81  */
  82 class PciDev : public DmaDevice
  83 {
  84     class PciConfigPort : public SimpleTimingPort
  85     {
  86       protected:
  87         PciDev *device;
  88
  89         virtual Tick recvAtomic(PacketPtr pkt);
  90
  91         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  92                                             AddrRangeList &snoop);
  93
  94         Platform *platform;
  95
  96         int busId;
  97         int deviceId;
  98         int functionId;
  99
 100         Addr configAddr;
 101
 102       public:
 103         PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
 104                       Platform *p);
 105     };
 106
 107   public:
 108     struct Params : public DmaDevice::Params
 109     {
 110         /**
 111          * A pointer to the object that contains the first 64 bytes of
 112          * config space
 113          */
 114         PciConfigData *configData;
 115
 116         /** The bus number we are on */
 117         uint32_t busNum;
 118
 119         /** The device number we have */
 120         uint32_t deviceNum;
 121
 122         /** The function number */
 123         uint32_t functionNum;
 124
 125         /** The latency for pio accesses. */
 126         Tick pio_delay;
 127
 128         /** The latency for a config access. */
 129         Tick config_delay;
 130     };
 131
 132   public:
 133     const Params *params() const { return (const Params *)_params; }
 134
 135   protected:
 136     /** The current config space. Unlike the PciConfigData this is
 137      * updated during simulation while continues to reflect what was
 138      * in the config file.
 139      */
 140     PCIConfig config;
 141
 142     /** The size of the BARs */
 143     uint32_t BARSize[6];
 144
 145     /** The current address mapping of the BARs */
 146     Addr BARAddrs[6];
 147
 148     /**
 149      * Does the given address lie within the space mapped by the given
 150      * base address register?
 151      */
 152     bool
 153     isBAR(Addr addr, int bar) const
 154     {
 155         assert(bar >= 0 && bar < 6);
 156         return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar];
 157     }
 158
 159     /**
 160      * Which base address register (if any) maps the given address?
 161      * @return The BAR number (0-5 inclusive), or -1 if none.
 162      */
 163     int
 164     getBAR(Addr addr)
 165     {
 166         for (int i = 0; i <= 5; ++i)
 167             if (isBAR(addr, i))
 168                 return i;
 169
 170         return -1;
 171     }
 172
 173     /**
 174      * Which base address register (if any) maps the given address?
 175      * @param addr The address to check.
 176      * @retval bar The BAR number (0-5 inclusive),
 177      *             only valid if return value is true.
 178      * @retval offs The offset from the base address,
 179      *              only valid if return value is true.
 180      * @return True iff address maps to a base address register's region.
 181      */
 182     bool
 183     getBAR(Addr addr, int &bar, Addr &offs)
 184     {
 185         int b = getBAR(addr);
 186         if (b < 0)
 187             return false;
 188
 189         offs = addr - BARAddrs[b];
 190         bar = b;
 191         return true;
 192     }
 193
 194   protected:
 195     Platform *plat;
 196     PciConfigData *configData;
 197     Tick pioDelay;
 198     Tick configDelay;
 199     PciConfigPort *configPort;
 200
 201     /**
 202      * Write to the PCI config space data that is stored locally. This may be
 203      * overridden by the device but at some point it will eventually call this
 204      * for normal operations that it does not need to override.
 205      * @param pkt packet containing the write the offset into config space
 206      */
 207     virtual Tick writeConfig(PacketPtr pkt);
 208
 209
 210     /**
 211      * Read from the PCI config space data that is stored locally. This may be
 212      * overridden by the device but at some point it will eventually call this
 213      * for normal operations that it does not need to override.
 214      * @param pkt packet containing the write the offset into config space
 215      */
 216     virtual Tick readConfig(PacketPtr pkt);
 217
 218   public:
 219     Addr pciToDma(Addr pciAddr) const
 220     { return plat->pciToDma(pciAddr); }
 221
 222     void
 223     intrPost()
 224     { plat->postPciInt(letoh(configData->config.interruptLine)); }
 225
 226     void
 227     intrClear()
 228     { plat->clearPciInt(letoh(configData->config.interruptLine)); }
 229
 230     uint8_t
 231     interruptLine()
 232     { return letoh(configData->config.interruptLine); }
 233
 234     /** return the address ranges that this device responds to.
 235      * @params range_list range list to populate with ranges
 236      */
 237     void addressRanges(AddrRangeList &range_list);
 238
 239     /**
 240      * Constructor for PCI Dev. This function copies data from the
 241      * config file object PCIConfigData and registers the device with
 242      * a PciConfigAll object.
 243      */
 244     PciDev(Params *params);
 245
 246     virtual void init();
 247
 248     /**
 249      * Serialize this object to the given output stream.
 250      * @param os The stream to serialize to.
 251      */
 252     virtual void serialize(std::ostream &os);
 253
 254     /**
 255      * Reconstruct the state of this object from a checkpoint.
 256      * @param cp The checkpoint use.
 257      * @param section The section name of this object
 258      */
 259     virtual void unserialize(Checkpoint *cp, const std::string &section);
 260
 261
 262     virtual unsigned int drain(Event *de);
 263
 264     virtual Port *getPort(const std::string &if_name, int idx = -1)
 265     {
 266         if (if_name == "config") {
 267             if (configPort != NULL)
 268                 panic("pciconfig port already connected to.");
 269             configPort = new PciConfigPort(this, params()->busNum,
 270                     params()->deviceNum, params()->functionNum,
 271                     params()->platform);
 272             return configPort;
 273         }
 274         return DmaDevice::getPort(if_name, idx);
 275     }
 276
 277 };
 278 #endif // __DEV_PCIDEV_HH__