847fb07d03ba0d5c6d00c760a3caabae72eb0715
[gem5.git] / src / dev / pcidev.hh
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Nathan Binkert
31 */
32
33 /* @file
34 * Interface for devices using PCI configuration
35 */
36
37 #ifndef __DEV_PCIDEV_HH__
38 #define __DEV_PCIDEV_HH__
39
40 #include "dev/io_device.hh"
41 #include "dev/pcireg.h"
42 #include "dev/platform.hh"
43
44 #define BAR_IO_MASK 0x3
45 #define BAR_MEM_MASK 0xF
46 #define BAR_IO_SPACE_BIT 0x1
47 #define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
48 #define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
49
50
51 /**
52 * This class encapulates the first 64 bytes of a singles PCI
53 * devices config space that in configured by the configuration file.
54 */
55 class PciConfigData : public SimObject
56 {
57 public:
58 /**
59 * Constructor to initialize the devices config space to 0.
60 */
61 PciConfigData(const std::string &name)
62 : SimObject(name)
63 {
64 memset(config.data, 0, sizeof(config.data));
65 memset(BARAddrs, 0, sizeof(BARAddrs));
66 memset(BARSize, 0, sizeof(BARSize));
67 }
68
69 /** The first 64 bytes */
70 PCIConfig config;
71
72 /** The size of the BARs */
73 uint32_t BARSize[6];
74
75 /** The addresses of the BARs */
76 Addr BARAddrs[6];
77 };
78
79
80 /**
81 * PCI device, base implemnation is only config space.
82 */
83 class PciDev : public DmaDevice
84 {
85 class PciConfigPort : public PioPort
86 {
87 protected:
88 PciDev *device;
89
90 virtual bool recvTiming(Packet *pkt);
91
92 virtual Tick recvAtomic(Packet *pkt);
93
94 virtual void recvFunctional(Packet *pkt) ;
95
96 virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
97
98 Platform *platform;
99
100 int busId;
101 int deviceId;
102 int functionId;
103
104 Addr configAddr;
105
106 public:
107 PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
108 Platform *p);
109
110 friend class PioPort::SendEvent;
111 };
112
113 public:
114 struct Params : public PioDevice::Params
115 {
116 /**
117 * A pointer to the object that contains the first 64 bytes of
118 * config space
119 */
120 PciConfigData *configData;
121
122 /** The bus number we are on */
123 uint32_t busNum;
124
125 /** The device number we have */
126 uint32_t deviceNum;
127
128 /** The function number */
129 uint32_t functionNum;
130
131 /** The latency for pio accesses. */
132 Tick pio_delay;
133
134 /** The latency for a config access. */
135 Tick config_delay;
136 };
137
138 public:
139 const Params *params() const { return (const Params *)_params; }
140
141 protected:
142 /** The current config space. Unlike the PciConfigData this is
143 * updated during simulation while continues to reflect what was
144 * in the config file.
145 */
146 PCIConfig config;
147
148 /** The size of the BARs */
149 uint32_t BARSize[6];
150
151 /** The current address mapping of the BARs */
152 Addr BARAddrs[6];
153
154 bool
155 isBAR(Addr addr, int bar) const
156 {
157 assert(bar >= 0 && bar < 6);
158 return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar];
159 }
160
161 int
162 getBAR(Addr addr)
163 {
164 for (int i = 0; i <= 5; ++i)
165 if (isBAR(addr, i))
166 return i;
167
168 return -1;
169 }
170
171 bool
172 getBAR(Addr paddr, Addr &daddr, int &bar)
173 {
174 int b = getBAR(paddr);
175 if (b < 0)
176 return false;
177
178 daddr = paddr - BARAddrs[b];
179 bar = b;
180 return true;
181 }
182
183 protected:
184 Platform *plat;
185 PciConfigData *configData;
186 Tick pioDelay;
187 Tick configDelay;
188 PciConfigPort *configPort;
189
190 /**
191 * Write to the PCI config space data that is stored locally. This may be
192 * overridden by the device but at some point it will eventually call this
193 * for normal operations that it does not need to override.
194 * @param pkt packet containing the write the offset into config space
195 */
196 virtual Tick writeConfig(Packet *pkt);
197
198
199 /**
200 * Read from the PCI config space data that is stored locally. This may be
201 * overridden by the device but at some point it will eventually call this
202 * for normal operations that it does not need to override.
203 * @param pkt packet containing the write the offset into config space
204 */
205 virtual Tick readConfig(Packet *pkt);
206
207 public:
208 Addr pciToDma(Addr pciAddr) const
209 { return plat->pciToDma(pciAddr); }
210
211 void
212 intrPost()
213 { plat->postPciInt(letoh(configData->config.interruptLine)); }
214
215 void
216 intrClear()
217 { plat->clearPciInt(letoh(configData->config.interruptLine)); }
218
219 uint8_t
220 interruptLine()
221 { return letoh(configData->config.interruptLine); }
222
223 /** return the address ranges that this device responds to.
224 * @params range_list range list to populate with ranges
225 */
226 void addressRanges(AddrRangeList &range_list);
227
228 /** Do a PCI Configspace memory access. */
229 Tick recvConfig(Packet *pkt)
230 { return pkt->isRead() ? readConfig(pkt) : writeConfig(pkt); }
231
232 /**
233 * Constructor for PCI Dev. This function copies data from the
234 * config file object PCIConfigData and registers the device with
235 * a PciConfigAll object.
236 */
237 PciDev(Params *params);
238
239 virtual void init();
240
241 /**
242 * Serialize this object to the given output stream.
243 * @param os The stream to serialize to.
244 */
245 virtual void serialize(std::ostream &os);
246
247 /**
248 * Reconstruct the state of this object from a checkpoint.
249 * @param cp The checkpoint use.
250 * @param section The section name of this object
251 */
252 virtual void unserialize(Checkpoint *cp, const std::string &section);
253
254
255 virtual unsigned int drain(Event *de);
256
257 virtual Port *getPort(const std::string &if_name, int idx = -1)
258 {
259 if (if_name == "config") {
260 if (configPort != NULL)
261 panic("pciconfig port already connected to.");
262 configPort = new PciConfigPort(this, params()->busNum,
263 params()->deviceNum, params()->functionNum,
264 params()->platform);
265 return configPort;
266 }
267 return DmaDevice::getPort(if_name, idx);
268 }
269
270 };
271 #endif // __DEV_PCIDEV_HH__