src/dev/pcidev.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  *          Andrew Schultz
  30  *          Nathan Binkert
  31  */
  32
  33 /* @file
  34  * Interface for devices using PCI configuration
  35  */
  36
  37 #ifndef __DEV_PCIDEV_HH__
  38 #define __DEV_PCIDEV_HH__
  39
  40 #include <cstring>
  41
  42 #include "dev/io_device.hh"
  43 #include "dev/pcireg.h"
  44 #include "dev/platform.hh"
  45 #include "params/PciDevice.hh"
  46 #include "sim/byteswap.hh"
  47
  48 #define BAR_IO_MASK 0x3
  49 #define BAR_MEM_MASK 0xF
  50 #define BAR_IO_SPACE_BIT 0x1
  51 #define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
  52 #define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
  53
  54
  55
  56 /**
  57  * PCI device, base implementation is only config space.
  58  */
  59 class PciDev : public DmaDevice
  60 {
  61     class PciConfigPort : public SimpleTimingPort
  62     {
  63       protected:
  64         PciDev *device;
  65
  66         virtual Tick recvAtomic(PacketPtr pkt);
  67
  68         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  69                                             bool &snoop);
  70
  71         Platform *platform;
  72
  73         int busId;
  74         int deviceId;
  75         int functionId;
  76
  77         Addr configAddr;
  78
  79       public:
  80         PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
  81                       Platform *p);
  82     };
  83
  84   public:
  85     typedef PciDeviceParams Params;
  86     const Params *
  87     params() const
  88     {
  89         return dynamic_cast<const Params *>(_params);
  90     }
  91
  92   protected:
  93     /** The current config space.  */
  94     PCIConfig config;
  95
  96     /** The size of the BARs */
  97     uint32_t BARSize[6];
  98
  99     /** The current address mapping of the BARs */
 100     Addr BARAddrs[6];
 101
 102     /**
 103      * Does the given address lie within the space mapped by the given
 104      * base address register?
 105      */
 106     bool
 107     isBAR(Addr addr, int bar) const
 108     {
 109         assert(bar >= 0 && bar < 6);
 110         return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar];
 111     }
 112
 113     /**
 114      * Which base address register (if any) maps the given address?
 115      * @return The BAR number (0-5 inclusive), or -1 if none.
 116      */
 117     int
 118     getBAR(Addr addr)
 119     {
 120         for (int i = 0; i <= 5; ++i)
 121             if (isBAR(addr, i))
 122                 return i;
 123
 124         return -1;
 125     }
 126
 127     /**
 128      * Which base address register (if any) maps the given address?
 129      * @param addr The address to check.
 130      * @retval bar The BAR number (0-5 inclusive),
 131      *             only valid if return value is true.
 132      * @retval offs The offset from the base address,
 133      *              only valid if return value is true.
 134      * @return True iff address maps to a base address register's region.
 135      */
 136     bool
 137     getBAR(Addr addr, int &bar, Addr &offs)
 138     {
 139         int b = getBAR(addr);
 140         if (b < 0)
 141             return false;
 142
 143         offs = addr - BARAddrs[b];
 144         bar = b;
 145         return true;
 146     }
 147
 148   protected:
 149     Platform *plat;
 150     Tick pioDelay;
 151     Tick configDelay;
 152     PciConfigPort *configPort;
 153
 154     /**
 155      * Write to the PCI config space data that is stored locally. This may be
 156      * overridden by the device but at some point it will eventually call this
 157      * for normal operations that it does not need to override.
 158      * @param pkt packet containing the write the offset into config space
 159      */
 160     virtual Tick writeConfig(PacketPtr pkt);
 161
 162
 163     /**
 164      * Read from the PCI config space data that is stored locally. This may be
 165      * overridden by the device but at some point it will eventually call this
 166      * for normal operations that it does not need to override.
 167      * @param pkt packet containing the write the offset into config space
 168      */
 169     virtual Tick readConfig(PacketPtr pkt);
 170
 171   public:
 172     Addr pciToDma(Addr pciAddr) const
 173     { return plat->pciToDma(pciAddr); }
 174
 175     void
 176     intrPost()
 177     { plat->postPciInt(letoh(config.interruptLine)); }
 178
 179     void
 180     intrClear()
 181     { plat->clearPciInt(letoh(config.interruptLine)); }
 182
 183     uint8_t
 184     interruptLine()
 185     { return letoh(config.interruptLine); }
 186
 187     /** return the address ranges that this device responds to.
 188      * @params range_list range list to populate with ranges
 189      */
 190     void addressRanges(AddrRangeList &range_list);
 191
 192     /**
 193      * Constructor for PCI Dev. This function copies data from the
 194      * config file object PCIConfigData and registers the device with
 195      * a PciConfigAll object.
 196      */
 197     PciDev(const Params *params);
 198
 199     virtual void init();
 200
 201     /**
 202      * Serialize this object to the given output stream.
 203      * @param os The stream to serialize to.
 204      */
 205     virtual void serialize(std::ostream &os);
 206
 207     /**
 208      * Reconstruct the state of this object from a checkpoint.
 209      * @param cp The checkpoint use.
 210      * @param section The section name of this object
 211      */
 212     virtual void unserialize(Checkpoint *cp, const std::string &section);
 213
 214
 215     virtual unsigned int drain(Event *de);
 216
 217     virtual Port *getPort(const std::string &if_name, int idx = -1)
 218     {
 219         if (if_name == "config") {
 220             if (configPort != NULL)
 221                 panic("pciconfig port already connected to.");
 222             configPort = new PciConfigPort(this, params()->pci_bus,
 223                     params()->pci_dev, params()->pci_func,
 224                     params()->platform);
 225             return configPort;
 226         }
 227         return DmaDevice::getPort(if_name, idx);
 228     }
 229
 230 };
 231 #endif // __DEV_PCIDEV_HH__