src/dev/pcireg.h

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Nathan Binkert
  41  *          Miguel Serrano
  42  */
  43
  44 /* @file
  45  * Device register definitions for a device's PCI config space
  46  */
  47
  48 #ifndef __PCIREG_H__
  49 #define __PCIREG_H__
  50
  51 #include <sys/types.h>
  52
  53 #include "base/bitfield.hh"
  54 #include "base/bitunion.hh"
  55
  56 union PCIConfig {
  57     uint8_t data[64];
  58
  59     struct {
  60         uint16_t vendor;
  61         uint16_t device;
  62         uint16_t command;
  63         uint16_t status;
  64         uint8_t revision;
  65         uint8_t progIF;
  66         uint8_t subClassCode;
  67         uint8_t classCode;
  68         uint8_t cacheLineSize;
  69         uint8_t latencyTimer;
  70         uint8_t headerType;
  71         uint8_t bist;
  72         uint32_t baseAddr[6];
  73         uint32_t cardbusCIS;
  74         uint16_t subsystemVendorID;
  75         uint16_t subsystemID;
  76         uint32_t expansionROM;
  77         uint8_t capabilityPtr;
  78         // Was 8 bytes in the legacy PCI spec, but to support PCIe
  79         // this field is now 7 bytes with PCIe's addition of the
  80         // capability list pointer.
  81         uint8_t reserved[7];
  82         uint8_t interruptLine;
  83         uint8_t interruptPin;
  84         uint8_t minimumGrant;
  85         uint8_t maximumLatency;
  86     };
  87 };
  88
  89 // Common PCI offsets
  90 #define PCI_VENDOR_ID           0x00    // Vendor ID                    ro
  91 #define PCI_DEVICE_ID           0x02    // Device ID                    ro
  92 #define PCI_COMMAND             0x04    // Command                      rw
  93 #define PCI_STATUS              0x06    // Status                       rw
  94 #define PCI_REVISION_ID         0x08    // Revision ID                  ro
  95 #define PCI_CLASS_CODE          0x09    // Class Code                   ro
  96 #define PCI_SUB_CLASS_CODE      0x0A    // Sub Class Code               ro
  97 #define PCI_BASE_CLASS_CODE     0x0B    // Base Class Code              ro
  98 #define PCI_CACHE_LINE_SIZE     0x0C    // Cache Line Size              ro+
  99 #define PCI_LATENCY_TIMER       0x0D    // Latency Timer                ro+
 100 #define PCI_HEADER_TYPE         0x0E    // Header Type                  ro
 101 #define PCI_BIST                0x0F    // Built in self test           rw
 102
 103 // some pci command reg bitfields
 104 #define PCI_CMD_BME     0x04 // Bus master function enable
 105 #define PCI_CMD_MSE     0x02 // Memory Space Access enable
 106 #define PCI_CMD_IOSE    0x01 // I/O space enable
 107
 108 // Type 0 PCI offsets
 109 #define PCI0_BASE_ADDR0         0x10    // Base Address 0               rw
 110 #define PCI0_BASE_ADDR1         0x14    // Base Address 1               rw
 111 #define PCI0_BASE_ADDR2         0x18    // Base Address 2               rw
 112 #define PCI0_BASE_ADDR3         0x1C    // Base Address 3               rw
 113 #define PCI0_BASE_ADDR4         0x20    // Base Address 4               rw
 114 #define PCI0_BASE_ADDR5         0x24    // Base Address 5               rw
 115 #define PCI0_CIS                0x28    // CardBus CIS Pointer          ro
 116 #define PCI0_SUB_VENDOR_ID      0x2C    // Sub-Vendor ID                ro
 117 #define PCI0_SUB_SYSTEM_ID      0x2E    // Sub-System ID                ro
 118 #define PCI0_ROM_BASE_ADDR      0x30    // Expansion ROM Base Address   rw
 119 #define PCI0_CAP_PTR            0x34    // Capability list pointer      ro
 120 #define PCI0_RESERVED           0x35
 121 #define PCI0_INTERRUPT_LINE     0x3C    // Interrupt Line               rw
 122 #define PCI0_INTERRUPT_PIN      0x3D    // Interrupt Pin                ro
 123 #define PCI0_MINIMUM_GRANT      0x3E    // Maximum Grant                ro
 124 #define PCI0_MAXIMUM_LATENCY    0x3F    // Maximum Latency              ro
 125
 126 // Type 1 PCI offsets
 127 #define PCI1_BASE_ADDR0         0x10    // Base Address 0               rw
 128 #define PCI1_BASE_ADDR1         0x14    // Base Address 1               rw
 129 #define PCI1_PRI_BUS_NUM        0x18    // Primary Bus Number           rw
 130 #define PCI1_SEC_BUS_NUM        0x19    // Secondary Bus Number         rw
 131 #define PCI1_SUB_BUS_NUM        0x1A    // Subordinate Bus Number       rw
 132 #define PCI1_SEC_LAT_TIMER      0x1B    // Secondary Latency Timer      ro+
 133 #define PCI1_IO_BASE            0x1C    // I/O Base                     rw
 134 #define PCI1_IO_LIMIT           0x1D    // I/O Limit                    rw
 135 #define PCI1_SECONDARY_STATUS   0x1E    // Secondary Status             rw
 136 #define PCI1_MEM_BASE           0x20    // Memory Base                  rw
 137 #define PCI1_MEM_LIMIT          0x22    // Memory Limit                 rw
 138 #define PCI1_PRF_MEM_BASE       0x24    // Prefetchable Memory Base     rw
 139 #define PCI1_PRF_MEM_LIMIT      0x26    // Prefetchable Memory Limit    rw
 140 #define PCI1_PRF_BASE_UPPER     0x28    // Prefetchable Base Upper 32   rw
 141 #define PCI1_PRF_LIMIT_UPPER    0x2C    // Prefetchable Limit Upper 32  rw
 142 #define PCI1_IO_BASE_UPPER      0x30    // I/O Base Upper 16 bits       rw
 143 #define PCI1_IO_LIMIT_UPPER     0x32    // I/O Limit Upper 16 bits      rw
 144 #define PCI1_RESERVED           0x34    // Reserved                     ro
 145 #define PCI1_ROM_BASE_ADDR      0x38    // Expansion ROM Base Address   rw
 146 #define PCI1_INTR_LINE          0x3C    // Interrupt Line               rw
 147 #define PCI1_INTR_PIN           0x3D    // Interrupt Pin                ro
 148 #define PCI1_BRIDGE_CTRL        0x3E    // Bridge Control               rw
 149
 150 // Device specific offsets
 151 #define PCI_DEVICE_SPECIFIC             0x40    // 192 bytes
 152 #define PCI_CONFIG_SIZE         0xFF
 153
 154 // Some Vendor IDs
 155 #define PCI_VENDOR_DEC                  0x1011
 156 #define PCI_VENDOR_NCR                  0x101A
 157 #define PCI_VENDOR_QLOGIC               0x1077
 158 #define PCI_VENDOR_SIMOS                0x1291
 159
 160 // Some Product IDs
 161 #define PCI_PRODUCT_DEC_PZA             0x0008
 162 #define PCI_PRODUCT_NCR_810             0x0001
 163 #define PCI_PRODUCT_QLOGIC_ISP1020      0x1020
 164 #define PCI_PRODUCT_SIMOS_SIMOS         0x1291
 165 #define PCI_PRODUCT_SIMOS_ETHER         0x1292
 166
 167 /**
 168  * PCIe capability list offsets internal to the entry.
 169  * Actual offsets in the PCI config space are defined in
 170  * the python files setting up the system.
 171  */
 172 #define PMCAP_ID 0x00
 173 #define PMCAP_PC 0x02
 174 #define PMCAP_PMCS 0x04
 175 #define PMCAP_SIZE 0x06
 176
 177 #define MSICAP_ID 0x00
 178 #define MSICAP_MC 0x02
 179 #define MSICAP_MA 0x04
 180 #define MSICAP_MUA 0x08
 181 #define MSICAP_MD 0x0C
 182 #define MSICAP_MMASK 0x10
 183 #define MSICAP_MPEND 0x14
 184 #define MSICAP_SIZE 0x18
 185
 186 #define MSIXCAP_ID 0x00
 187 #define MSIXCAP_MXC 0x02
 188 #define MSIXCAP_MTAB 0x04
 189 #define MSIXCAP_MPBA 0x08
 190 #define MSIXCAP_SIZE 0x0C
 191
 192 #define PXCAP_ID 0x00
 193 #define PXCAP_PXCAP 0x02
 194 #define PXCAP_PXDCAP 0x04
 195 #define PXCAP_PXDC 0x08
 196 #define PXCAP_PXDS 0x0A
 197 #define PXCAP_PXLCAP 0x0C
 198 #define PXCAP_PXLC 0x10
 199 #define PXCAP_PXLS 0x12
 200 #define PXCAP_PXDCAP2 0x24
 201 #define PXCAP_PXDC2 0x28
 202 #define PXCAP_SIZE 0x30
 203
 204 /** @struct PMCAP
 205  *  Defines the Power Management capability register and all its associated
 206  *  bitfields for a PCIe device.
 207  */
 208 struct PMCAP {
 209     BitUnion16(PID)
 210         Bitfield<7,0>   cid;
 211         Bitfield<15,8>  next;
 212     EndBitUnion(PID)
 213     PID pid;
 214
 215     BitUnion16(PC)
 216         Bitfield<2,0>   vs;
 217         Bitfield<3>     pmec;
 218         Bitfield<4>     reserved;
 219         Bitfield<5>     dsi;
 220         Bitfield<8,6>   auxc;
 221         Bitfield<9>     d1s;
 222         Bitfield<10>    d2s;
 223         Bitfield<15,11> psup;
 224     EndBitUnion(PC)
 225     PC pc;
 226
 227     BitUnion16(PMCS)
 228         Bitfield<1,0>   ps;
 229         Bitfield<2>     reserved0;
 230         Bitfield<3>     nsfrst;
 231         Bitfield<7,4>   reserved1;
 232         Bitfield<8>     pmee;
 233         Bitfield<12,9>  dse;
 234         Bitfield<14,13> dsc;
 235         Bitfield<15>    pmes;
 236     EndBitUnion(PMCS)
 237     PMCS pmcs;
 238 };
 239
 240 /** @struct MSICAP
 241  *  Defines the MSI Capability register and its associated bitfields for
 242  *  the a PCI/PCIe device.  Both the MSI capability and the MSIX capability
 243  *  can be filled in if a device model supports both, but only 1 of
 244  *  MSI/MSIX/INTx interrupt mode can be selected at a given time.
 245  */
 246 struct MSICAP {
 247     BitUnion16(MID)
 248         Bitfield<7,0>   cid;
 249         Bitfield<15,8>  next;
 250     EndBitUnion(MID)
 251     MID mid;
 252
 253     BitUnion16(MC)
 254         Bitfield<0>     msie;
 255         Bitfield<3,1>   mmc;
 256         Bitfield<6,4>   mme;
 257         Bitfield<7>     c64;
 258         Bitfield<8>     pvm;
 259         Bitfield<15,9>  reserved;
 260     EndBitUnion(MC)
 261     MC mc;
 262
 263     BitUnion32(MA)
 264         Bitfield<1,0>   reserved;
 265         Bitfield<31,2>  addr;
 266     EndBitUnion(MA)
 267     MA ma;
 268
 269     uint32_t mua;
 270
 271     BitUnion16(MD)
 272         Bitfield<15,0> data;
 273     EndBitUnion(MD)
 274     MD md;
 275
 276     uint32_t mmask;
 277     uint32_t mpend;
 278 };
 279
 280 /** @struct MSIX
 281  *  Defines the MSI-X Capability register and its associated bitfields for
 282  *  a PCIe device.
 283  */
 284 struct MSIXCAP {
 285     BitUnion16(MXID)
 286         Bitfield<7,0>   cid;
 287         Bitfield<15,8>  next;
 288     EndBitUnion(MXID)
 289     MXID mxid;
 290
 291     BitUnion16(MXC)
 292         Bitfield<10,0>  ts;
 293         Bitfield<13,11> reserved;
 294         Bitfield<14>    fm;
 295         Bitfield<15>    mxe;
 296     EndBitUnion(MXC)
 297     MXC mxc;
 298
 299     BitUnion32(MTAB)
 300         Bitfield<31,3>  to;
 301         Bitfield<2,0>   tbir;
 302     EndBitUnion(MTAB)
 303     MTAB mtab;
 304
 305     BitUnion32(MPBA)
 306         Bitfield<2,0>   pbir;
 307         Bitfield<31,3>  pbao;
 308     EndBitUnion(MPBA)
 309     MPBA mpba;
 310 };
 311
 312 union MSIXTable {
 313     struct {
 314         uint32_t addr_lo;
 315         uint32_t addr_hi;
 316         uint32_t msg_data;
 317         uint32_t vec_ctrl;
 318     } fields;
 319     uint32_t data[4];
 320 };
 321
 322 #define MSIXVECS_PER_PBA 64
 323 struct MSIXPbaEntry {
 324     uint64_t bits;
 325 };
 326
 327 /** @struct PXCAP
 328  *  Defines the PCI Express capability register and its associated bitfields
 329  *  for a PCIe device.
 330  */
 331 struct PXCAP {
 332     BitUnion16(PXID)
 333         Bitfield<7,0>   cid;
 334         Bitfield<15,8>  next;
 335     EndBitUnion(PXID)
 336     PXID pxid;
 337
 338     BitUnion16(_PXCAP)
 339         Bitfield<3,0>   ver;
 340         Bitfield<7,4>   dpt;
 341         Bitfield<8>     si;
 342         Bitfield<13,9>  imn;
 343         Bitfield<15,14> reserved;
 344     EndBitUnion(_PXCAP)
 345     _PXCAP pxcap;
 346
 347     BitUnion32(PXDCAP)
 348         Bitfield<2,0>   mps;
 349         Bitfield<4,3>   pfs;
 350         Bitfield<5>     etfs;
 351         Bitfield<8,6>   l0sl;
 352         Bitfield<11,9>  l1l;
 353         Bitfield<14,12> reserved0;
 354         Bitfield<15>    rer;
 355         Bitfield<17,16> reserved1;
 356         Bitfield<25,18> csplv;
 357         Bitfield<27,26> cspls;
 358         Bitfield<28>    flrc;
 359         Bitfield<31,29> reserved2;
 360     EndBitUnion(PXDCAP)
 361     PXDCAP pxdcap;
 362
 363     BitUnion16(PXDC)
 364         Bitfield<0>     cere;
 365         Bitfield<1>     nfere;
 366         Bitfield<2>     fere;
 367         Bitfield<3>     urre;
 368         Bitfield<4>     ero;
 369         Bitfield<7,5>   mps;
 370         Bitfield<8>     ete;
 371         Bitfield<9>     pfe;
 372         Bitfield<10>    appme;
 373         Bitfield<11>    ens;
 374         Bitfield<14,12> mrrs;
 375         Bitfield<15>    func_reset;
 376     EndBitUnion(PXDC)
 377     PXDC pxdc;
 378
 379     BitUnion16(PXDS)
 380         Bitfield<0>     ced;
 381         Bitfield<1>     nfed;
 382         Bitfield<2>     fed;
 383         Bitfield<3>     urd;
 384         Bitfield<4>     apd;
 385         Bitfield<5>     tp;
 386         Bitfield<15,6>  reserved;
 387     EndBitUnion(PXDS)
 388     PXDS pxds;
 389
 390     BitUnion32(PXLCAP)
 391         Bitfield<3,0>   sls;
 392         Bitfield<9,4>   mlw;
 393         Bitfield<11,10> aspms;
 394         Bitfield<14,12> l0sel;
 395         Bitfield<17,15> l1el;
 396         Bitfield<18>    cpm;
 397         Bitfield<19>    sderc;
 398         Bitfield<20>    dllla;
 399         Bitfield<21>    lbnc;
 400         Bitfield<23,22> reserved;
 401         Bitfield<31,24> pn;
 402     EndBitUnion(PXLCAP)
 403     PXLCAP pxlcap;
 404
 405     BitUnion16(PXLC)
 406         Bitfield<1,0>   aspmc;
 407         Bitfield<2>     reserved0;
 408         Bitfield<3>     rcb;
 409         Bitfield<5,4>   reserved1;
 410         Bitfield<6>     ccc;
 411         Bitfield<7>     es;
 412         Bitfield<8>     ecpm;
 413         Bitfield<9>     hawd;
 414         Bitfield<15,10> reserved2;
 415     EndBitUnion(PXLC)
 416     PXLC pxlc;
 417
 418     BitUnion16(PXLS)
 419         Bitfield<3,0>   cls;
 420         Bitfield<9,4>   nlw;
 421         Bitfield<11,10> reserved0;
 422         Bitfield<12>    slot_clk_config;
 423         Bitfield<15,13> reserved1;
 424     EndBitUnion(PXLS)
 425     PXLS pxls;
 426
 427     BitUnion32(PXDCAP2)
 428         Bitfield<3,0>   ctrs;
 429         Bitfield<4>     ctds;
 430         Bitfield<5>     arifs;
 431         Bitfield<6>     aors;
 432         Bitfield<7>     aocs32;
 433         Bitfield<8>     aocs64;
 434         Bitfield<9>     ccs128;
 435         Bitfield<10>    nprpr;
 436         Bitfield<11>    ltrs;
 437         Bitfield<13,12> tphcs;
 438         Bitfield<17,14> reserved0;
 439         Bitfield<19,18> obffs;
 440         Bitfield<20>    effs;
 441         Bitfield<21>    eetps;
 442         Bitfield<23,22> meetp;
 443         Bitfield<31,24> reserved1;
 444     EndBitUnion(PXDCAP2)
 445     PXDCAP2 pxdcap2;
 446
 447     BitUnion32(PXDC2)
 448         Bitfield<3,0>   ctv;
 449         Bitfield<4>     ctd;
 450         Bitfield<9,5>   reserved0;
 451         Bitfield<10>    ltrme;
 452         Bitfield<12,11> reserved1;
 453         Bitfield<14,13> obffe;
 454         Bitfield<31,15> reserved2;
 455     EndBitUnion(PXDC2)
 456     PXDC2 pxdc2;
 457 };
 458 #endif // __PCIREG_H__