2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
35 #include "arch/vtophys.hh"
36 #include "base/compiler.hh"
37 #include "base/debug.hh"
38 #include "base/inet.hh"
39 #include "base/types.hh"
40 #include "config/the_isa.hh"
41 #include "cpu/intr_control.hh"
42 #include "cpu/thread_context.hh"
43 #include "debug/EthernetAll.hh"
44 #include "dev/etherlink.hh"
45 #include "dev/sinic.hh"
46 #include "mem/packet.hh"
47 #include "mem/packet_access.hh"
48 #include "sim/eventq.hh"
49 #include "sim/stats.hh"
53 using namespace TheISA
;
57 const char *RxStateStrings
[] =
66 const char *TxStateStrings
[] =
76 ///////////////////////////////////////////////////////////////////////
80 Base::Base(const Params
*p
)
81 : PciDev(p
), rxEnable(false), txEnable(false), clock(p
->clock
),
82 intrDelay(p
->intr_delay
), intrTick(0), cpuIntrEnable(false),
83 cpuPendingIntr(false), intrEvent(0), interface(NULL
)
87 Device::Device(const Params
*p
)
88 : Base(p
), rxUnique(0), txUnique(0),
89 virtualRegs(p
->virtual_count
< 1 ? 1 : p
->virtual_count
),
90 rxFifo(p
->rx_fifo_size
), txFifo(p
->tx_fifo_size
),
91 rxKickTick(0), txKickTick(0),
92 txEvent(this), rxDmaEvent(this), txDmaEvent(this),
93 dmaReadDelay(p
->dma_read_delay
), dmaReadFactor(p
->dma_read_factor
),
94 dmaWriteDelay(p
->dma_write_delay
), dmaWriteFactor(p
->dma_write_factor
)
96 interface
= new Interface(name() + ".int0", this);
108 .name(name() + ".rxBytes")
109 .desc("Bytes Received")
114 .name(name() + ".rxBandwidth")
115 .desc("Receive Bandwidth (bits/s)")
121 .name(name() + ".rxPackets")
122 .desc("Number of Packets Received")
127 .name(name() + ".rxPPS")
128 .desc("Packet Reception Rate (packets/s)")
134 .name(name() + ".rxIpPackets")
135 .desc("Number of IP Packets Received")
140 .name(name() + ".rxTcpPackets")
141 .desc("Number of Packets Received")
146 .name(name() + ".rxUdpPackets")
147 .desc("Number of UDP Packets Received")
152 .name(name() + ".rxIpChecksums")
153 .desc("Number of rx IP Checksums done by device")
159 .name(name() + ".rxTcpChecksums")
160 .desc("Number of rx TCP Checksums done by device")
166 .name(name() + ".rxUdpChecksums")
167 .desc("Number of rx UDP Checksums done by device")
173 .name(name() + ".totBandwidth")
174 .desc("Total Bandwidth (bits/s)")
180 .name(name() + ".totPackets")
181 .desc("Total Packets")
187 .name(name() + ".totBytes")
194 .name(name() + ".totPPS")
195 .desc("Total Tranmission Rate (packets/s)")
201 .name(name() + ".txBytes")
202 .desc("Bytes Transmitted")
207 .name(name() + ".txBandwidth")
208 .desc("Transmit Bandwidth (bits/s)")
214 .name(name() + ".txPackets")
215 .desc("Number of Packets Transmitted")
220 .name(name() + ".txPPS")
221 .desc("Packet Tranmission Rate (packets/s)")
227 .name(name() + ".txIpPackets")
228 .desc("Number of IP Packets Transmitted")
233 .name(name() + ".txTcpPackets")
234 .desc("Number of TCP Packets Transmitted")
239 .name(name() + ".txUdpPackets")
240 .desc("Number of Packets Transmitted")
245 .name(name() + ".txIpChecksums")
246 .desc("Number of tx IP Checksums done by device")
252 .name(name() + ".txTcpChecksums")
253 .desc("Number of tx TCP Checksums done by device")
259 .name(name() + ".txUdpChecksums")
260 .desc("Number of tx UDP Checksums done by device")
265 txBandwidth
= txBytes
* Stats::constant(8) / simSeconds
;
266 rxBandwidth
= rxBytes
* Stats::constant(8) / simSeconds
;
267 totBandwidth
= txBandwidth
+ rxBandwidth
;
268 totBytes
= txBytes
+ rxBytes
;
269 totPackets
= txPackets
+ rxPackets
;
270 txPacketRate
= txPackets
/ simSeconds
;
271 rxPacketRate
= rxPackets
/ simSeconds
;
273 _maxVnicDistance
= 0;
276 .name(name() + ".maxVnicDistance")
277 .desc("maximum vnic distance")
281 .name(name() + ".totalVnicDistance")
282 .desc("total vnic distance")
285 .name(name() + ".numVnicDistance")
286 .desc("number of vnic distance measurements")
290 .name(name() + ".avgVnicDistance")
291 .desc("average vnic distance")
294 avgVnicDistance
= totalVnicDistance
/ numVnicDistance
;
300 _maxVnicDistance
= 0;
304 Device::getEthPort(const std::string
&if_name
, int idx
)
306 if (if_name
== "interface") {
307 if (interface
->getPeer())
308 panic("interface already connected to\n");
317 Device::prepareIO(int cpu
, int index
)
319 int size
= virtualRegs
.size();
321 panic("Trying to access a vnic that doesn't exist %d > %d\n",
325 //add stats for head of line blocking
326 //add stats for average fifo length
327 //add stats for average number of vnics busy
330 Device::prepareRead(int cpu
, int index
)
332 using namespace Regs
;
333 prepareIO(cpu
, index
);
335 VirtualReg
&vnic
= virtualRegs
[index
];
337 // update rx registers
338 uint64_t rxdone
= vnic
.RxDone
;
339 rxdone
= set_RxDone_Packets(rxdone
, rxFifo
.countPacketsAfter(rxFifoPtr
));
340 rxdone
= set_RxDone_Empty(rxdone
, rxFifo
.empty());
341 rxdone
= set_RxDone_High(rxdone
, rxFifo
.size() > regs
.RxFifoHigh
);
342 rxdone
= set_RxDone_NotHigh(rxdone
, rxLow
);
343 regs
.RxData
= vnic
.RxData
;
344 regs
.RxDone
= rxdone
;
345 regs
.RxWait
= rxdone
;
347 // update tx regsiters
348 uint64_t txdone
= vnic
.TxDone
;
349 txdone
= set_TxDone_Packets(txdone
, txFifo
.packets());
350 txdone
= set_TxDone_Full(txdone
, txFifo
.avail() < regs
.TxMaxCopy
);
351 txdone
= set_TxDone_Low(txdone
, txFifo
.size() < regs
.TxFifoLow
);
352 regs
.TxData
= vnic
.TxData
;
353 regs
.TxDone
= txdone
;
354 regs
.TxWait
= txdone
;
358 if (!rxFifo
.empty()) {
359 int vnic
= rxFifo
.begin()->priv
;
360 if (vnic
!= -1 && virtualRegs
[vnic
].rxPacketOffset
> 0)
364 regs
.RxStatus
= set_RxStatus_Head(regs
.RxStatus
, head
);
365 regs
.RxStatus
= set_RxStatus_Busy(regs
.RxStatus
, rxBusyCount
);
366 regs
.RxStatus
= set_RxStatus_Mapped(regs
.RxStatus
, rxMappedCount
);
367 regs
.RxStatus
= set_RxStatus_Dirty(regs
.RxStatus
, rxDirtyCount
);
371 Device::prepareWrite(int cpu
, int index
)
373 prepareIO(cpu
, index
);
377 * I/O read of device register
380 Device::read(PacketPtr pkt
)
382 assert(config
.command
& PCI_CMD_MSE
);
383 assert(pkt
->getAddr() >= BARAddrs
[0] && pkt
->getSize() < BARSize
[0]);
385 int cpu
= pkt
->req
->contextId();
386 Addr daddr
= pkt
->getAddr() - BARAddrs
[0];
387 Addr index
= daddr
>> Regs::VirtualShift
;
388 Addr raddr
= daddr
& Regs::VirtualMask
;
392 if (!regValid(raddr
))
393 panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d",
394 cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
396 const Regs::Info
&info
= regInfo(raddr
);
398 panic("read %s (write only): "
399 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
400 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
402 panic("read %s (invalid size): "
403 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
404 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
406 prepareRead(cpu
, index
);
408 uint64_t value M5_VAR_USED
= 0;
409 if (pkt
->getSize() == 4) {
410 uint32_t reg
= regData32(raddr
);
415 if (pkt
->getSize() == 8) {
416 uint64_t reg
= regData64(raddr
);
422 "read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n",
423 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize(), value
);
425 // reading the interrupt status register has the side effect of
427 if (raddr
== Regs::IntrStatus
)
434 * IPR read of device register
437 Device::iprRead(Addr daddr, int cpu, uint64_t &result)
439 if (!regValid(daddr))
440 panic("invalid address: da=%#x", daddr);
442 const Regs::Info &info = regInfo(daddr);
444 panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu, daddr);
446 DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n",
447 info.name, cpu, daddr);
452 result = regData32(daddr);
455 result = regData64(daddr);
457 DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
458 info.name, cpu, result);
464 * I/O write of device register
467 Device::write(PacketPtr pkt
)
469 assert(config
.command
& PCI_CMD_MSE
);
470 assert(pkt
->getAddr() >= BARAddrs
[0] && pkt
->getSize() < BARSize
[0]);
472 int cpu
= pkt
->req
->contextId();
473 Addr daddr
= pkt
->getAddr() - BARAddrs
[0];
474 Addr index
= daddr
>> Regs::VirtualShift
;
475 Addr raddr
= daddr
& Regs::VirtualMask
;
477 if (!regValid(raddr
))
478 panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
479 cpu
, daddr
, pkt
->getAddr(), pkt
->getSize());
481 const Regs::Info
&info
= regInfo(raddr
);
483 panic("write %s (read only): "
484 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
485 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
487 if (pkt
->getSize() != info
.size
)
488 panic("write %s (invalid size): "
489 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
490 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
492 VirtualReg
&vnic
= virtualRegs
[index
];
495 "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
496 info
.name
, index
, cpu
, info
.size
== 4 ? pkt
->get
<uint32_t>() :
497 pkt
->get
<uint64_t>(), daddr
, pkt
->getAddr(), pkt
->getSize());
499 prepareWrite(cpu
, index
);
503 changeConfig(pkt
->get
<uint32_t>());
507 command(pkt
->get
<uint32_t>());
510 case Regs::IntrStatus
:
511 devIntrClear(regs
.IntrStatus
& pkt
->get
<uint32_t>());
515 devIntrChangeMask(pkt
->get
<uint32_t>());
519 if (Regs::get_RxDone_Busy(vnic
.RxDone
))
520 panic("receive machine busy with another request! rxState=%s",
521 RxStateStrings
[rxState
]);
523 vnic
.rxUnique
= rxUnique
++;
524 vnic
.RxDone
= Regs::RxDone_Busy
;
525 vnic
.RxData
= pkt
->get
<uint64_t>();
528 if (Regs::get_RxData_Vaddr(pkt
->get
<uint64_t>())) {
529 panic("vtophys not implemented in newmem");
531 Addr vaddr
= Regs::get_RxData_Addr(reg64
);
532 Addr paddr
= vtophys(req
->xc
, vaddr
);
533 DPRINTF(EthernetPIO
, "write RxData vnic %d (rxunique %d): "
534 "vaddr=%#x, paddr=%#x\n",
535 index
, vnic
.rxUnique
, vaddr
, paddr
);
537 vnic
.RxData
= Regs::set_RxData_Addr(vnic
.RxData
, paddr
);
540 DPRINTF(EthernetPIO
, "write RxData vnic %d (rxunique %d)\n",
541 index
, vnic
.rxUnique
);
544 if (vnic
.rxIndex
== rxFifo
.end()) {
545 DPRINTF(EthernetPIO
, "request new packet...appending to rxList\n");
546 rxList
.push_back(index
);
548 DPRINTF(EthernetPIO
, "packet exists...appending to rxBusy\n");
549 rxBusy
.push_back(index
);
552 if (rxEnable
&& (rxState
== rxIdle
|| rxState
== rxFifoBlock
)) {
553 rxState
= rxFifoBlock
;
559 if (Regs::get_TxDone_Busy(vnic
.TxDone
))
560 panic("transmit machine busy with another request! txState=%s",
561 TxStateStrings
[txState
]);
563 vnic
.txUnique
= txUnique
++;
564 vnic
.TxDone
= Regs::TxDone_Busy
;
566 if (Regs::get_TxData_Vaddr(pkt
->get
<uint64_t>())) {
567 panic("vtophys won't work here in newmem.\n");
569 Addr vaddr
= Regs::get_TxData_Addr(reg64
);
570 Addr paddr
= vtophys(req
->xc
, vaddr
);
571 DPRINTF(EthernetPIO
, "write TxData vnic %d (txunique %d): "
572 "vaddr=%#x, paddr=%#x\n",
573 index
, vnic
.txUnique
, vaddr
, paddr
);
575 vnic
.TxData
= Regs::set_TxData_Addr(vnic
.TxData
, paddr
);
578 DPRINTF(EthernetPIO
, "write TxData vnic %d (txunique %d)\n",
579 index
, vnic
.txUnique
);
582 if (txList
.empty() || txList
.front() != index
)
583 txList
.push_back(index
);
584 if (txEnable
&& txState
== txIdle
&& txList
.front() == index
) {
585 txState
= txFifoBlock
;
595 Device::devIntrPost(uint32_t interrupts
)
597 if ((interrupts
& Regs::Intr_Res
))
598 panic("Cannot set a reserved interrupt");
600 regs
.IntrStatus
|= interrupts
;
602 DPRINTF(EthernetIntr
,
603 "interrupt written to intStatus: intr=%#x status=%#x mask=%#x\n",
604 interrupts
, regs
.IntrStatus
, regs
.IntrMask
);
606 interrupts
= regs
.IntrStatus
& regs
.IntrMask
;
608 // Intr_RxHigh is special, we only signal it if we've emptied the fifo
609 // and then filled it above the high watermark
613 interrupts
&= ~Regs::Intr_RxHigh
;
615 // Intr_TxLow is special, we only signal it if we've filled up the fifo
616 // and then dropped below the low watermark
620 interrupts
&= ~Regs::Intr_TxLow
;
623 Tick when
= curTick();
624 if ((interrupts
& Regs::Intr_NoDelay
) == 0)
631 Device::devIntrClear(uint32_t interrupts
)
633 if ((interrupts
& Regs::Intr_Res
))
634 panic("Cannot clear a reserved interrupt");
636 regs
.IntrStatus
&= ~interrupts
;
638 DPRINTF(EthernetIntr
,
639 "interrupt cleared from intStatus: intr=%x status=%x mask=%x\n",
640 interrupts
, regs
.IntrStatus
, regs
.IntrMask
);
642 if (!(regs
.IntrStatus
& regs
.IntrMask
))
647 Device::devIntrChangeMask(uint32_t newmask
)
649 if (regs
.IntrMask
== newmask
)
652 regs
.IntrMask
= newmask
;
654 DPRINTF(EthernetIntr
,
655 "interrupt mask changed: intStatus=%x intMask=%x masked=%x\n",
656 regs
.IntrStatus
, regs
.IntrMask
, regs
.IntrStatus
& regs
.IntrMask
);
658 if (regs
.IntrStatus
& regs
.IntrMask
)
659 cpuIntrPost(curTick());
665 Base::cpuIntrPost(Tick when
)
667 // If the interrupt you want to post is later than an interrupt
668 // already scheduled, just let it post in the coming one and don't
670 // HOWEVER, must be sure that the scheduled intrTick is in the
671 // future (this was formerly the source of a bug)
673 * @todo this warning should be removed and the intrTick code should
676 assert(when
>= curTick());
677 assert(intrTick
>= curTick() || intrTick
== 0);
678 if (!cpuIntrEnable
) {
679 DPRINTF(EthernetIntr
, "interrupts not enabled.\n",
684 if (when
> intrTick
&& intrTick
!= 0) {
685 DPRINTF(EthernetIntr
, "don't need to schedule event...intrTick=%d\n",
691 if (intrTick
< curTick()) {
693 intrTick
= curTick();
696 DPRINTF(EthernetIntr
, "going to schedule an interrupt for intrTick=%d\n",
701 intrEvent
= new IntrEvent(this, true);
702 schedule(intrEvent
, intrTick
);
708 assert(intrTick
== curTick());
710 // Whether or not there's a pending interrupt, we don't care about
715 // Don't send an interrupt if there's already one
716 if (cpuPendingIntr
) {
717 DPRINTF(EthernetIntr
,
718 "would send an interrupt now, but there's already pending\n");
721 cpuPendingIntr
= true;
723 DPRINTF(EthernetIntr
, "posting interrupt\n");
741 cpuPendingIntr
= false;
743 DPRINTF(EthernetIntr
, "clearing cchip interrupt\n");
748 Base::cpuIntrPending() const
749 { return cpuPendingIntr
; }
752 Device::changeConfig(uint32_t newconf
)
754 uint32_t changed
= regs
.Config
^ newconf
;
758 regs
.Config
= newconf
;
760 if ((changed
& Regs::Config_IntEn
)) {
761 cpuIntrEnable
= regs
.Config
& Regs::Config_IntEn
;
763 if (regs
.IntrStatus
& regs
.IntrMask
)
764 cpuIntrPost(curTick());
770 if ((changed
& Regs::Config_TxEn
)) {
771 txEnable
= regs
.Config
& Regs::Config_TxEn
;
776 if ((changed
& Regs::Config_RxEn
)) {
777 rxEnable
= regs
.Config
& Regs::Config_RxEn
;
784 Device::command(uint32_t command
)
786 if (command
& Regs::Command_Intr
)
787 devIntrPost(Regs::Intr_Soft
);
789 if (command
& Regs::Command_Reset
)
796 using namespace Regs
;
798 memset(®s
, 0, sizeof(regs
));
801 if (params()->rx_thread
)
802 regs
.Config
|= Config_RxThread
;
803 if (params()->tx_thread
)
804 regs
.Config
|= Config_TxThread
;
806 regs
.Config
|= Config_RSS
;
807 if (params()->zero_copy
)
808 regs
.Config
|= Config_ZeroCopy
;
809 if (params()->delay_copy
)
810 regs
.Config
|= Config_DelayCopy
;
811 if (params()->virtual_addr
)
812 regs
.Config
|= Config_Vaddr
;
814 if (params()->delay_copy
&& params()->zero_copy
)
815 panic("Can't delay copy and zero copy");
817 regs
.IntrMask
= Intr_Soft
| Intr_RxHigh
| Intr_RxPacket
| Intr_TxLow
;
818 regs
.RxMaxCopy
= params()->rx_max_copy
;
819 regs
.TxMaxCopy
= params()->tx_max_copy
;
820 regs
.ZeroCopySize
= params()->zero_copy_size
;
821 regs
.ZeroCopyMark
= params()->zero_copy_threshold
;
822 regs
.VirtualCount
= params()->virtual_count
;
823 regs
.RxMaxIntr
= params()->rx_max_intr
;
824 regs
.RxFifoSize
= params()->rx_fifo_size
;
825 regs
.TxFifoSize
= params()->tx_fifo_size
;
826 regs
.RxFifoLow
= params()->rx_fifo_low_mark
;
827 regs
.TxFifoLow
= params()->tx_fifo_threshold
;
828 regs
.RxFifoHigh
= params()->rx_fifo_threshold
;
829 regs
.TxFifoHigh
= params()->tx_fifo_high_mark
;
830 regs
.HwAddr
= params()->hardware_address
;
832 if (regs
.RxMaxCopy
< regs
.ZeroCopyMark
)
833 panic("Must be able to copy at least as many bytes as the threshold");
835 if (regs
.ZeroCopySize
>= regs
.ZeroCopyMark
)
836 panic("The number of bytes to copy must be less than the threshold");
850 rxFifoPtr
= rxFifo
.end();
856 int size
= virtualRegs
.size();
858 virtualRegs
.resize(size
);
859 for (int i
= 0; i
< size
; ++i
)
860 virtualRegs
[i
].rxIndex
= rxFifo
.end();
866 assert(rxState
== rxCopy
);
867 rxState
= rxCopyDone
;
868 DPRINTF(EthernetDMA
, "end rx dma write paddr=%#x len=%d\n",
869 rxDmaAddr
, rxDmaLen
);
870 DDUMP(EthernetData
, rxDmaData
, rxDmaLen
);
872 // If the transmit state machine has a pending DMA, let it go first
873 if (txState
== txBeginCopy
)
882 VirtualReg
*vnic
= NULL
;
884 DPRINTF(EthernetSM
, "rxKick: rxState=%s (rxFifo.size=%d)\n",
885 RxStateStrings
[rxState
], rxFifo
.size());
887 if (rxKickTick
> curTick()) {
888 DPRINTF(EthernetSM
, "rxKick: exiting, can't run till %d\n",
895 if (rxState
== rxIdle
)
898 if (rxActive
== -1) {
899 if (rxState
!= rxFifoBlock
)
900 panic("no active vnic while in state %s", RxStateStrings
[rxState
]);
902 DPRINTF(EthernetSM
, "processing rxState=%s\n",
903 RxStateStrings
[rxState
]);
905 vnic
= &virtualRegs
[rxActive
];
907 "processing rxState=%s for vnic %d (rxunique %d)\n",
908 RxStateStrings
[rxState
], rxActive
, vnic
->rxUnique
);
913 if (DTRACE(EthernetSM
)) {
914 PacketFifo::iterator end
= rxFifo
.end();
915 int size
= virtualRegs
.size();
916 for (int i
= 0; i
< size
; ++i
) {
917 VirtualReg
*vn
= &virtualRegs
[i
];
918 bool busy
= Regs::get_RxDone_Busy(vn
->RxDone
);
919 if (vn
->rxIndex
!= end
) {
921 bool dirty
= vn
->rxPacketOffset
> 0;
925 status
= "busy,dirty";
934 "vnic %d %s (rxunique %d), packet %d, slack %d\n",
935 i
, status
, vn
->rxUnique
,
936 rxFifo
.countPacketsBefore(vn
->rxIndex
),
940 DPRINTF(EthernetSM
, "vnic %d unmapped (rxunique %d)\n",
946 if (!rxBusy
.empty()) {
947 rxActive
= rxBusy
.front();
949 vnic
= &virtualRegs
[rxActive
];
951 if (vnic
->rxIndex
== rxFifo
.end())
952 panic("continuing vnic without packet\n");
955 "continue processing for vnic %d (rxunique %d)\n",
956 rxActive
, vnic
->rxUnique
);
958 rxState
= rxBeginCopy
;
960 int vnic_distance
= rxFifo
.countPacketsBefore(vnic
->rxIndex
);
961 totalVnicDistance
+= vnic_distance
;
962 numVnicDistance
+= 1;
963 if (vnic_distance
> _maxVnicDistance
) {
964 maxVnicDistance
= vnic_distance
;
965 _maxVnicDistance
= vnic_distance
;
971 if (rxFifoPtr
== rxFifo
.end()) {
972 DPRINTF(EthernetSM
, "receive waiting for data. Nothing to do.\n");
977 panic("Not idle, but nothing to do!");
979 assert(!rxFifo
.empty());
981 rxActive
= rxList
.front();
983 vnic
= &virtualRegs
[rxActive
];
986 "processing new packet for vnic %d (rxunique %d)\n",
987 rxActive
, vnic
->rxUnique
);
989 // Grab a new packet from the fifo.
990 vnic
->rxIndex
= rxFifoPtr
++;
991 vnic
->rxIndex
->priv
= rxActive
;
992 vnic
->rxPacketOffset
= 0;
993 vnic
->rxPacketBytes
= vnic
->rxIndex
->packet
->length
;
994 assert(vnic
->rxPacketBytes
);
997 vnic
->rxDoneData
= 0;
998 /* scope for variables */ {
999 IpPtr
ip(vnic
->rxIndex
->packet
);
1001 DPRINTF(Ethernet
, "ID is %d\n", ip
->id());
1002 vnic
->rxDoneData
|= Regs::RxDone_IpPacket
;
1004 if (cksum(ip
) != 0) {
1005 DPRINTF(EthernetCksum
, "Rx IP Checksum Error\n");
1006 vnic
->rxDoneData
|= Regs::RxDone_IpError
;
1012 "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
1013 tcp
->sport(), tcp
->dport(), tcp
->seq(),
1015 vnic
->rxDoneData
|= Regs::RxDone_TcpPacket
;
1017 if (cksum(tcp
) != 0) {
1018 DPRINTF(EthernetCksum
, "Rx TCP Checksum Error\n");
1019 vnic
->rxDoneData
|= Regs::RxDone_TcpError
;
1022 vnic
->rxDoneData
|= Regs::RxDone_UdpPacket
;
1024 if (cksum(udp
) != 0) {
1025 DPRINTF(EthernetCksum
, "Rx UDP Checksum Error\n");
1026 vnic
->rxDoneData
|= Regs::RxDone_UdpError
;
1031 rxState
= rxBeginCopy
;
1035 if (dmaPending() || getState() != Running
)
1038 rxDmaAddr
= params()->platform
->pciToDma(
1039 Regs::get_RxData_Addr(vnic
->RxData
));
1040 rxDmaLen
= min
<unsigned>(Regs::get_RxData_Len(vnic
->RxData
),
1041 vnic
->rxPacketBytes
);
1044 * if we're doing zero/delay copy and we're below the fifo
1045 * threshold, see if we should try to do the zero/defer copy
1047 if ((Regs::get_Config_ZeroCopy(regs
.Config
) ||
1048 Regs::get_Config_DelayCopy(regs
.Config
)) &&
1049 !Regs::get_RxData_NoDelay(vnic
->RxData
) && rxLow
) {
1050 if (rxDmaLen
> regs
.ZeroCopyMark
)
1051 rxDmaLen
= regs
.ZeroCopySize
;
1053 rxDmaData
= vnic
->rxIndex
->packet
->data
+ vnic
->rxPacketOffset
;
1055 if (rxDmaAddr
== 1LL) {
1056 rxState
= rxCopyDone
;
1060 dmaWrite(rxDmaAddr
, rxDmaLen
, &rxDmaEvent
, rxDmaData
);
1064 DPRINTF(EthernetSM
, "receive machine still copying\n");
1068 vnic
->RxDone
= vnic
->rxDoneData
;
1069 vnic
->RxDone
|= Regs::RxDone_Complete
;
1072 if (vnic
->rxPacketBytes
== rxDmaLen
) {
1073 if (vnic
->rxPacketOffset
)
1076 // Packet is complete. Indicate how many bytes were copied
1077 vnic
->RxDone
= Regs::set_RxDone_CopyLen(vnic
->RxDone
, rxDmaLen
);
1080 "rxKick: packet complete on vnic %d (rxunique %d)\n",
1081 rxActive
, vnic
->rxUnique
);
1082 rxFifo
.remove(vnic
->rxIndex
);
1083 vnic
->rxIndex
= rxFifo
.end();
1086 if (!vnic
->rxPacketOffset
)
1089 vnic
->rxPacketBytes
-= rxDmaLen
;
1090 vnic
->rxPacketOffset
+= rxDmaLen
;
1091 vnic
->RxDone
|= Regs::RxDone_More
;
1092 vnic
->RxDone
= Regs::set_RxDone_CopyLen(vnic
->RxDone
,
1093 vnic
->rxPacketBytes
);
1095 "rxKick: packet not complete on vnic %d (rxunique %d): "
1097 rxActive
, vnic
->rxUnique
, vnic
->rxPacketBytes
);
1101 rxState
= rxBusy
.empty() && rxList
.empty() ? rxIdle
: rxFifoBlock
;
1103 if (rxFifo
.empty()) {
1104 devIntrPost(Regs::Intr_RxEmpty
);
1108 if (rxFifo
.size() < regs
.RxFifoLow
)
1111 if (rxFifo
.size() > regs
.RxFifoHigh
)
1114 devIntrPost(Regs::Intr_RxDMA
);
1118 panic("Invalid rxState!");
1121 DPRINTF(EthernetSM
, "entering next rxState=%s\n",
1122 RxStateStrings
[rxState
]);
1128 * @todo do we want to schedule a future kick?
1130 DPRINTF(EthernetSM
, "rx state machine exited rxState=%s\n",
1131 RxStateStrings
[rxState
]);
1137 assert(txState
== txCopy
);
1138 txState
= txCopyDone
;
1139 DPRINTF(EthernetDMA
, "tx dma read paddr=%#x len=%d\n",
1140 txDmaAddr
, txDmaLen
);
1141 DDUMP(EthernetData
, txDmaData
, txDmaLen
);
1143 // If the receive state machine has a pending DMA, let it go first
1144 if (rxState
== rxBeginCopy
)
1153 if (txFifo
.empty()) {
1154 DPRINTF(Ethernet
, "nothing to transmit\n");
1158 uint32_t interrupts
;
1159 EthPacketPtr packet
= txFifo
.front();
1160 if (!interface
->sendPacket(packet
)) {
1161 DPRINTF(Ethernet
, "Packet Transmit: failed txFifo available %d\n",
1168 if (DTRACE(Ethernet
)) {
1171 DPRINTF(Ethernet
, "ID is %d\n", ip
->id());
1175 "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
1176 tcp
->sport(), tcp
->dport(), tcp
->seq(),
1183 DDUMP(EthernetData
, packet
->data
, packet
->length
);
1184 txBytes
+= packet
->length
;
1187 DPRINTF(Ethernet
, "Packet Transmit: successful txFifo Available %d\n",
1190 interrupts
= Regs::Intr_TxPacket
;
1191 if (txFifo
.size() < regs
.TxFifoLow
)
1192 interrupts
|= Regs::Intr_TxLow
;
1193 devIntrPost(interrupts
);
1200 DPRINTF(EthernetSM
, "txKick: txState=%s (txFifo.size=%d)\n",
1201 TxStateStrings
[txState
], txFifo
.size());
1203 if (txKickTick
> curTick()) {
1204 DPRINTF(EthernetSM
, "txKick: exiting, can't run till %d\n",
1210 if (txState
== txIdle
)
1213 assert(!txList
.empty());
1214 vnic
= &virtualRegs
[txList
.front()];
1218 assert(Regs::get_TxDone_Busy(vnic
->TxDone
));
1220 // Grab a new packet from the fifo.
1221 txPacket
= new EthPacketData(16384);
1225 if (txFifo
.avail() - txPacket
->length
<
1226 Regs::get_TxData_Len(vnic
->TxData
)) {
1227 DPRINTF(EthernetSM
, "transmit fifo full. Nothing to do.\n");
1231 txState
= txBeginCopy
;
1235 if (dmaPending() || getState() != Running
)
1238 txDmaAddr
= params()->platform
->pciToDma(
1239 Regs::get_TxData_Addr(vnic
->TxData
));
1240 txDmaLen
= Regs::get_TxData_Len(vnic
->TxData
);
1241 txDmaData
= txPacket
->data
+ txPacketOffset
;
1244 dmaRead(txDmaAddr
, txDmaLen
, &txDmaEvent
, txDmaData
);
1248 DPRINTF(EthernetSM
, "transmit machine still copying\n");
1252 vnic
->TxDone
= txDmaLen
| Regs::TxDone_Complete
;
1253 txPacket
->length
+= txDmaLen
;
1254 if ((vnic
->TxData
& Regs::TxData_More
)) {
1255 txPacketOffset
+= txDmaLen
;
1257 devIntrPost(Regs::Intr_TxDMA
);
1261 assert(txPacket
->length
<= txFifo
.avail());
1262 if ((vnic
->TxData
& Regs::TxData_Checksum
)) {
1268 tcp
->sum(cksum(tcp
));
1275 udp
->sum(cksum(udp
));
1285 txFifo
.push(txPacket
);
1286 if (txFifo
.avail() < regs
.TxMaxCopy
) {
1287 devIntrPost(Regs::Intr_TxFull
);
1293 txState
= txList
.empty() ? txIdle
: txFifoBlock
;
1294 devIntrPost(Regs::Intr_TxDMA
);
1298 panic("Invalid txState!");
1301 DPRINTF(EthernetSM
, "entering next txState=%s\n",
1302 TxStateStrings
[txState
]);
1308 * @todo do we want to schedule a future kick?
1310 DPRINTF(EthernetSM
, "tx state machine exited txState=%s\n",
1311 TxStateStrings
[txState
]);
1315 Device::transferDone()
1317 if (txFifo
.empty()) {
1318 DPRINTF(Ethernet
, "transfer complete: txFifo empty...nothing to do\n");
1322 DPRINTF(Ethernet
, "transfer complete: data in txFifo...schedule xmit\n");
1324 reschedule(txEvent
, curTick() + ticks(1), true);
1328 Device::rxFilter(const EthPacketPtr
&packet
)
1330 if (!Regs::get_Config_Filter(regs
.Config
))
1333 panic("receive filter not implemented\n");
1339 EthHdr
*eth
= packet
->eth();
1340 if (eth
->unicast()) {
1341 // If we're accepting all unicast addresses
1345 // If we make a perfect match
1346 if (acceptPerfect
&& params
->eaddr
== eth
.dst())
1349 if (acceptArp
&& eth
->type() == ETH_TYPE_ARP
)
1352 } else if (eth
->broadcast()) {
1353 // if we're accepting broadcasts
1354 if (acceptBroadcast
)
1357 } else if (eth
->multicast()) {
1358 // if we're accepting all multicasts
1359 if (acceptMulticast
)
1365 DPRINTF(Ethernet
, "rxFilter drop\n");
1366 DDUMP(EthernetData
, packet
->data
, packet
->length
);
1373 Device::recvPacket(EthPacketPtr packet
)
1375 rxBytes
+= packet
->length
;
1378 DPRINTF(Ethernet
, "Receiving packet from wire, rxFifo Available is %d\n",
1382 DPRINTF(Ethernet
, "receive disabled...packet dropped\n");
1386 if (rxFilter(packet
)) {
1387 DPRINTF(Ethernet
, "packet filtered...dropped\n");
1391 if (rxFifo
.size() >= regs
.RxFifoHigh
)
1392 devIntrPost(Regs::Intr_RxHigh
);
1394 if (!rxFifo
.push(packet
)) {
1396 "packet will not fit in receive buffer...packet dropped\n");
1400 // If we were at the last element, back up one ot go to the new
1401 // last element of the list.
1402 if (rxFifoPtr
== rxFifo
.end())
1405 devIntrPost(Regs::Intr_RxPacket
);
1413 SimObject::resume();
1415 // During drain we could have left the state machines in a waiting state and
1416 // they wouldn't get out until some other event occured to kick them.
1417 // This way they'll get out immediately
1422 //=====================================================================
1426 Base::serialize(std::ostream
&os
)
1428 // Serialize the PciDev base class
1429 PciDev::serialize(os
);
1431 SERIALIZE_SCALAR(rxEnable
);
1432 SERIALIZE_SCALAR(txEnable
);
1433 SERIALIZE_SCALAR(cpuIntrEnable
);
1436 * Keep track of pending interrupt status.
1438 SERIALIZE_SCALAR(intrTick
);
1439 SERIALIZE_SCALAR(cpuPendingIntr
);
1440 Tick intrEventTick
= 0;
1442 intrEventTick
= intrEvent
->when();
1443 SERIALIZE_SCALAR(intrEventTick
);
1447 Base::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1449 // Unserialize the PciDev base class
1450 PciDev::unserialize(cp
, section
);
1452 UNSERIALIZE_SCALAR(rxEnable
);
1453 UNSERIALIZE_SCALAR(txEnable
);
1454 UNSERIALIZE_SCALAR(cpuIntrEnable
);
1457 * Keep track of pending interrupt status.
1459 UNSERIALIZE_SCALAR(intrTick
);
1460 UNSERIALIZE_SCALAR(cpuPendingIntr
);
1462 UNSERIALIZE_SCALAR(intrEventTick
);
1463 if (intrEventTick
) {
1464 intrEvent
= new IntrEvent(this, true);
1465 schedule(intrEvent
, intrEventTick
);
1470 Device::serialize(std::ostream
&os
)
1474 // Serialize the PciDev base class
1475 Base::serialize(os
);
1477 if (rxState
== rxCopy
)
1478 panic("can't serialize with an in flight dma request rxState=%s",
1479 RxStateStrings
[rxState
]);
1481 if (txState
== txCopy
)
1482 panic("can't serialize with an in flight dma request txState=%s",
1483 TxStateStrings
[txState
]);
1486 * Serialize the device registers that could be modified by the OS.
1488 SERIALIZE_SCALAR(regs
.Config
);
1489 SERIALIZE_SCALAR(regs
.IntrStatus
);
1490 SERIALIZE_SCALAR(regs
.IntrMask
);
1491 SERIALIZE_SCALAR(regs
.RxData
);
1492 SERIALIZE_SCALAR(regs
.TxData
);
1495 * Serialize the virtual nic state
1497 int virtualRegsSize
= virtualRegs
.size();
1498 SERIALIZE_SCALAR(virtualRegsSize
);
1499 for (int i
= 0; i
< virtualRegsSize
; ++i
) {
1500 VirtualReg
*vnic
= &virtualRegs
[i
];
1502 std::string reg
= csprintf("vnic%d", i
);
1503 paramOut(os
, reg
+ ".RxData", vnic
->RxData
);
1504 paramOut(os
, reg
+ ".RxDone", vnic
->RxDone
);
1505 paramOut(os
, reg
+ ".TxData", vnic
->TxData
);
1506 paramOut(os
, reg
+ ".TxDone", vnic
->TxDone
);
1508 bool rxPacketExists
= vnic
->rxIndex
!= rxFifo
.end();
1509 paramOut(os
, reg
+ ".rxPacketExists", rxPacketExists
);
1510 if (rxPacketExists
) {
1512 PacketFifo::iterator i
= rxFifo
.begin();
1513 while (i
!= vnic
->rxIndex
) {
1514 assert(i
!= rxFifo
.end());
1519 paramOut(os
, reg
+ ".rxPacket", rxPacket
);
1520 paramOut(os
, reg
+ ".rxPacketOffset", vnic
->rxPacketOffset
);
1521 paramOut(os
, reg
+ ".rxPacketBytes", vnic
->rxPacketBytes
);
1523 paramOut(os
, reg
+ ".rxDoneData", vnic
->rxDoneData
);
1527 if (this->rxFifoPtr
!= rxFifo
.end())
1528 rxFifoPtr
= rxFifo
.countPacketsBefore(this->rxFifoPtr
);
1529 SERIALIZE_SCALAR(rxFifoPtr
);
1531 SERIALIZE_SCALAR(rxActive
);
1532 SERIALIZE_SCALAR(rxBusyCount
);
1533 SERIALIZE_SCALAR(rxDirtyCount
);
1534 SERIALIZE_SCALAR(rxMappedCount
);
1536 VirtualList::iterator i
, end
;
1537 for (count
= 0, i
= rxList
.begin(), end
= rxList
.end(); i
!= end
; ++i
)
1538 paramOut(os
, csprintf("rxList%d", count
++), *i
);
1539 int rxListSize
= count
;
1540 SERIALIZE_SCALAR(rxListSize
);
1542 for (count
= 0, i
= rxBusy
.begin(), end
= rxBusy
.end(); i
!= end
; ++i
)
1543 paramOut(os
, csprintf("rxBusy%d", count
++), *i
);
1544 int rxBusySize
= count
;
1545 SERIALIZE_SCALAR(rxBusySize
);
1547 for (count
= 0, i
= txList
.begin(), end
= txList
.end(); i
!= end
; ++i
)
1548 paramOut(os
, csprintf("txList%d", count
++), *i
);
1549 int txListSize
= count
;
1550 SERIALIZE_SCALAR(txListSize
);
1553 * Serialize rx state machine
1555 int rxState
= this->rxState
;
1556 SERIALIZE_SCALAR(rxState
);
1557 SERIALIZE_SCALAR(rxEmpty
);
1558 SERIALIZE_SCALAR(rxLow
);
1559 rxFifo
.serialize("rxFifo", os
);
1562 * Serialize tx state machine
1564 int txState
= this->txState
;
1565 SERIALIZE_SCALAR(txState
);
1566 SERIALIZE_SCALAR(txFull
);
1567 txFifo
.serialize("txFifo", os
);
1568 bool txPacketExists
= txPacket
;
1569 SERIALIZE_SCALAR(txPacketExists
);
1570 if (txPacketExists
) {
1571 txPacket
->serialize("txPacket", os
);
1572 SERIALIZE_SCALAR(txPacketOffset
);
1573 SERIALIZE_SCALAR(txPacketBytes
);
1577 * If there's a pending transmit, store the time so we can
1578 * reschedule it later
1580 Tick transmitTick
= txEvent
.scheduled() ? txEvent
.when() - curTick() : 0;
1581 SERIALIZE_SCALAR(transmitTick
);
1585 Device::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1587 // Unserialize the PciDev base class
1588 Base::unserialize(cp
, section
);
1591 * Unserialize the device registers that may have been written by the OS.
1593 UNSERIALIZE_SCALAR(regs
.Config
);
1594 UNSERIALIZE_SCALAR(regs
.IntrStatus
);
1595 UNSERIALIZE_SCALAR(regs
.IntrMask
);
1596 UNSERIALIZE_SCALAR(regs
.RxData
);
1597 UNSERIALIZE_SCALAR(regs
.TxData
);
1599 UNSERIALIZE_SCALAR(rxActive
);
1600 UNSERIALIZE_SCALAR(rxBusyCount
);
1601 UNSERIALIZE_SCALAR(rxDirtyCount
);
1602 UNSERIALIZE_SCALAR(rxMappedCount
);
1605 UNSERIALIZE_SCALAR(rxListSize
);
1607 for (int i
= 0; i
< rxListSize
; ++i
) {
1609 paramIn(cp
, section
, csprintf("rxList%d", i
), value
);
1610 rxList
.push_back(value
);
1614 UNSERIALIZE_SCALAR(rxBusySize
);
1616 for (int i
= 0; i
< rxBusySize
; ++i
) {
1618 paramIn(cp
, section
, csprintf("rxBusy%d", i
), value
);
1619 rxBusy
.push_back(value
);
1623 UNSERIALIZE_SCALAR(txListSize
);
1625 for (int i
= 0; i
< txListSize
; ++i
) {
1627 paramIn(cp
, section
, csprintf("txList%d", i
), value
);
1628 txList
.push_back(value
);
1632 * Unserialize rx state machine
1635 UNSERIALIZE_SCALAR(rxState
);
1636 UNSERIALIZE_SCALAR(rxEmpty
);
1637 UNSERIALIZE_SCALAR(rxLow
);
1638 this->rxState
= (RxState
) rxState
;
1639 rxFifo
.unserialize("rxFifo", cp
, section
);
1642 UNSERIALIZE_SCALAR(rxFifoPtr
);
1643 if (rxFifoPtr
>= 0) {
1644 this->rxFifoPtr
= rxFifo
.begin();
1645 for (int i
= 0; i
< rxFifoPtr
; ++i
)
1648 this->rxFifoPtr
= rxFifo
.end();
1652 * Unserialize tx state machine
1655 UNSERIALIZE_SCALAR(txState
);
1656 UNSERIALIZE_SCALAR(txFull
);
1657 this->txState
= (TxState
) txState
;
1658 txFifo
.unserialize("txFifo", cp
, section
);
1659 bool txPacketExists
;
1660 UNSERIALIZE_SCALAR(txPacketExists
);
1662 if (txPacketExists
) {
1663 txPacket
= new EthPacketData(16384);
1664 txPacket
->unserialize("txPacket", cp
, section
);
1665 UNSERIALIZE_SCALAR(txPacketOffset
);
1666 UNSERIALIZE_SCALAR(txPacketBytes
);
1670 * unserialize the virtual nic registers/state
1672 * this must be done after the unserialization of the rxFifo
1673 * because the packet iterators depend on the fifo being populated
1675 int virtualRegsSize
;
1676 UNSERIALIZE_SCALAR(virtualRegsSize
);
1677 virtualRegs
.clear();
1678 virtualRegs
.resize(virtualRegsSize
);
1679 for (int i
= 0; i
< virtualRegsSize
; ++i
) {
1680 VirtualReg
*vnic
= &virtualRegs
[i
];
1681 std::string reg
= csprintf("vnic%d", i
);
1683 paramIn(cp
, section
, reg
+ ".RxData", vnic
->RxData
);
1684 paramIn(cp
, section
, reg
+ ".RxDone", vnic
->RxDone
);
1685 paramIn(cp
, section
, reg
+ ".TxData", vnic
->TxData
);
1686 paramIn(cp
, section
, reg
+ ".TxDone", vnic
->TxDone
);
1688 vnic
->rxUnique
= rxUnique
++;
1689 vnic
->txUnique
= txUnique
++;
1691 bool rxPacketExists
;
1692 paramIn(cp
, section
, reg
+ ".rxPacketExists", rxPacketExists
);
1693 if (rxPacketExists
) {
1695 paramIn(cp
, section
, reg
+ ".rxPacket", rxPacket
);
1696 vnic
->rxIndex
= rxFifo
.begin();
1700 paramIn(cp
, section
, reg
+ ".rxPacketOffset",
1701 vnic
->rxPacketOffset
);
1702 paramIn(cp
, section
, reg
+ ".rxPacketBytes", vnic
->rxPacketBytes
);
1704 vnic
->rxIndex
= rxFifo
.end();
1706 paramIn(cp
, section
, reg
+ ".rxDoneData", vnic
->rxDoneData
);
1710 * If there's a pending transmit, reschedule it now
1713 UNSERIALIZE_SCALAR(transmitTick
);
1715 schedule(txEvent
, curTick() + transmitTick
);
1717 pioPort
->sendStatusChange(Port::RangeChange
);
1721 } // namespace Sinic
1724 SinicParams::create()
1726 return new Sinic::Device(this);