2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
35 #include "arch/vtophys.hh"
36 #include "base/inet.hh"
37 #include "cpu/thread_context.hh"
38 #include "cpu/intr_control.hh"
39 #include "dev/etherlink.hh"
40 #include "dev/sinic.hh"
41 #include "mem/packet.hh"
42 #include "mem/packet_access.hh"
43 #include "sim/debug.hh"
44 #include "sim/eventq.hh"
45 #include "sim/host.hh"
46 #include "sim/stats.hh"
49 using namespace TheISA
;
53 const char *RxStateStrings
[] =
62 const char *TxStateStrings
[] =
72 ///////////////////////////////////////////////////////////////////////
77 : PciDev(p
), rxEnable(false), txEnable(false), clock(p
->clock
),
78 intrDelay(p
->intr_delay
), intrTick(0), cpuIntrEnable(false),
79 cpuPendingIntr(false), intrEvent(0), interface(NULL
)
83 Device::Device(Params
*p
)
84 : Base(p
), rxUnique(0), txUnique(0),
85 virtualRegs(p
->virtual_count
< 1 ? 1 : p
->virtual_count
),
86 rxFifo(p
->rx_fifo_size
), txFifo(p
->tx_fifo_size
),
87 rxKickTick(0), txKickTick(0),
88 txEvent(this), rxDmaEvent(this), txDmaEvent(this),
89 dmaReadDelay(p
->dma_read_delay
), dmaReadFactor(p
->dma_read_factor
),
90 dmaWriteDelay(p
->dma_write_delay
), dmaWriteFactor(p
->dma_write_factor
)
103 .name(name() + ".rxBytes")
104 .desc("Bytes Received")
109 .name(name() + ".rxBandwidth")
110 .desc("Receive Bandwidth (bits/s)")
116 .name(name() + ".rxPackets")
117 .desc("Number of Packets Received")
122 .name(name() + ".rxPPS")
123 .desc("Packet Reception Rate (packets/s)")
129 .name(name() + ".rxIpPackets")
130 .desc("Number of IP Packets Received")
135 .name(name() + ".rxTcpPackets")
136 .desc("Number of Packets Received")
141 .name(name() + ".rxUdpPackets")
142 .desc("Number of UDP Packets Received")
147 .name(name() + ".rxIpChecksums")
148 .desc("Number of rx IP Checksums done by device")
154 .name(name() + ".rxTcpChecksums")
155 .desc("Number of rx TCP Checksums done by device")
161 .name(name() + ".rxUdpChecksums")
162 .desc("Number of rx UDP Checksums done by device")
168 .name(name() + ".totBandwidth")
169 .desc("Total Bandwidth (bits/s)")
175 .name(name() + ".totPackets")
176 .desc("Total Packets")
182 .name(name() + ".totBytes")
189 .name(name() + ".totPPS")
190 .desc("Total Tranmission Rate (packets/s)")
196 .name(name() + ".txBytes")
197 .desc("Bytes Transmitted")
202 .name(name() + ".txBandwidth")
203 .desc("Transmit Bandwidth (bits/s)")
209 .name(name() + ".txPackets")
210 .desc("Number of Packets Transmitted")
215 .name(name() + ".txPPS")
216 .desc("Packet Tranmission Rate (packets/s)")
222 .name(name() + ".txIpPackets")
223 .desc("Number of IP Packets Transmitted")
228 .name(name() + ".txTcpPackets")
229 .desc("Number of TCP Packets Transmitted")
234 .name(name() + ".txUdpPackets")
235 .desc("Number of Packets Transmitted")
240 .name(name() + ".txIpChecksums")
241 .desc("Number of tx IP Checksums done by device")
247 .name(name() + ".txTcpChecksums")
248 .desc("Number of tx TCP Checksums done by device")
254 .name(name() + ".txUdpChecksums")
255 .desc("Number of tx UDP Checksums done by device")
260 txBandwidth
= txBytes
* Stats::constant(8) / simSeconds
;
261 rxBandwidth
= rxBytes
* Stats::constant(8) / simSeconds
;
262 totBandwidth
= txBandwidth
+ rxBandwidth
;
263 totBytes
= txBytes
+ rxBytes
;
264 totPackets
= txPackets
+ rxPackets
;
265 txPacketRate
= txPackets
/ simSeconds
;
266 rxPacketRate
= rxPackets
/ simSeconds
;
270 Device::prepareIO(int cpu
, int index
)
272 int size
= virtualRegs
.size();
274 panic("Trying to access a vnic that doesn't exist %d > %d\n",
279 Device::prepareRead(int cpu
, int index
)
281 using namespace Regs
;
282 prepareIO(cpu
, index
);
284 VirtualReg
&vnic
= virtualRegs
[index
];
286 // update rx registers
287 uint64_t rxdone
= vnic
.RxDone
;
288 rxdone
= set_RxDone_Packets(rxdone
, rxFifo
.countPacketsAfter(rxFifoPtr
));
289 rxdone
= set_RxDone_Empty(rxdone
, rxFifo
.empty());
290 rxdone
= set_RxDone_High(rxdone
, rxFifo
.size() > regs
.RxFifoMark
);
291 rxdone
= set_RxDone_NotHigh(rxdone
, rxLow
);
292 regs
.RxData
= vnic
.RxData
;
293 regs
.RxDone
= rxdone
;
294 regs
.RxWait
= rxdone
;
296 // update tx regsiters
297 uint64_t txdone
= vnic
.TxDone
;
298 txdone
= set_TxDone_Packets(txdone
, txFifo
.packets());
299 txdone
= set_TxDone_Full(txdone
, txFifo
.avail() < regs
.TxMaxCopy
);
300 txdone
= set_TxDone_Low(txdone
, txFifo
.size() < regs
.TxFifoMark
);
301 regs
.TxData
= vnic
.TxData
;
302 regs
.TxDone
= txdone
;
303 regs
.TxWait
= txdone
;
307 Device::prepareWrite(int cpu
, int index
)
309 prepareIO(cpu
, index
);
313 * I/O read of device register
316 Device::read(PacketPtr pkt
)
318 assert(config
.command
& PCI_CMD_MSE
);
319 assert(pkt
->getAddr() >= BARAddrs
[0] && pkt
->getSize() < BARSize
[0]);
321 int cpu
= pkt
->req
->getCpuNum();
322 Addr daddr
= pkt
->getAddr() - BARAddrs
[0];
323 Addr index
= daddr
>> Regs::VirtualShift
;
324 Addr raddr
= daddr
& Regs::VirtualMask
;
328 if (!regValid(raddr
))
329 panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d",
330 cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
332 const Regs::Info
&info
= regInfo(raddr
);
334 panic("read %s (write only): "
335 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
336 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
338 panic("read %s (invalid size): "
339 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
340 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
342 prepareRead(cpu
, index
);
345 if (pkt
->getSize() == 4) {
346 uint32_t reg
= regData32(raddr
);
351 if (pkt
->getSize() == 8) {
352 uint64_t reg
= regData64(raddr
);
358 "read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n",
359 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize(), value
);
361 // reading the interrupt status register has the side effect of
363 if (raddr
== Regs::IntrStatus
)
370 * IPR read of device register
373 Device::iprRead(Addr daddr, int cpu, uint64_t &result)
375 if (!regValid(daddr))
376 panic("invalid address: da=%#x", daddr);
378 const Regs::Info &info = regInfo(daddr);
380 panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu, daddr);
382 DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n",
383 info.name, cpu, daddr);
388 result = regData32(daddr);
391 result = regData64(daddr);
393 DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
394 info.name, cpu, result);
400 * I/O write of device register
403 Device::write(PacketPtr pkt
)
405 assert(config
.command
& PCI_CMD_MSE
);
406 assert(pkt
->getAddr() >= BARAddrs
[0] && pkt
->getSize() < BARSize
[0]);
408 int cpu
= pkt
->req
->getCpuNum();
409 Addr daddr
= pkt
->getAddr() - BARAddrs
[0];
410 Addr index
= daddr
>> Regs::VirtualShift
;
411 Addr raddr
= daddr
& Regs::VirtualMask
;
413 if (!regValid(raddr
))
414 panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
415 cpu
, daddr
, pkt
->getAddr(), pkt
->getSize());
417 const Regs::Info
&info
= regInfo(raddr
);
419 panic("write %s (read only): "
420 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
421 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
423 if (pkt
->getSize() != info
.size
)
424 panic("write %s (invalid size): "
425 "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
426 info
.name
, cpu
, index
, daddr
, pkt
->getAddr(), pkt
->getSize());
428 VirtualReg
&vnic
= virtualRegs
[index
];
431 "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
432 info
.name
, index
, cpu
, info
.size
== 4 ? pkt
->get
<uint32_t>() :
433 pkt
->get
<uint64_t>(), daddr
, pkt
->getAddr(), pkt
->getSize());
435 prepareWrite(cpu
, index
);
439 changeConfig(pkt
->get
<uint32_t>());
443 command(pkt
->get
<uint32_t>());
446 case Regs::IntrStatus
:
447 devIntrClear(regs
.IntrStatus
& pkt
->get
<uint32_t>());
451 devIntrChangeMask(pkt
->get
<uint32_t>());
455 if (Regs::get_RxDone_Busy(vnic
.RxDone
))
456 panic("receive machine busy with another request! rxState=%s",
457 RxStateStrings
[rxState
]);
459 vnic
.rxUnique
= rxUnique
++;
460 vnic
.RxDone
= Regs::RxDone_Busy
;
461 vnic
.RxData
= pkt
->get
<uint64_t>();
463 if (Regs::get_RxData_Vaddr(pkt
->get
<uint64_t>())) {
464 panic("vtophys not implemented in newmem");
465 /* Addr vaddr = Regs::get_RxData_Addr(reg64);
466 Addr paddr = vtophys(req->xc, vaddr);
467 DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d): "
468 "vaddr=%#x, paddr=%#x\n",
469 index, vnic.rxUnique, vaddr, paddr);
471 vnic.RxData = Regs::set_RxData_Addr(vnic.RxData, paddr);*/
473 DPRINTF(EthernetPIO
, "write RxData vnic %d (rxunique %d)\n",
474 index
, vnic
.rxUnique
);
477 if (vnic
.rxPacket
== rxFifo
.end()) {
478 DPRINTF(EthernetPIO
, "request new packet...appending to rxList\n");
479 rxList
.push_back(index
);
481 DPRINTF(EthernetPIO
, "packet exists...appending to rxBusy\n");
482 rxBusy
.push_back(index
);
485 if (rxEnable
&& (rxState
== rxIdle
|| rxState
== rxFifoBlock
)) {
486 rxState
= rxFifoBlock
;
492 if (Regs::get_TxDone_Busy(vnic
.TxDone
))
493 panic("transmit machine busy with another request! txState=%s",
494 TxStateStrings
[txState
]);
496 vnic
.txUnique
= txUnique
++;
497 vnic
.TxDone
= Regs::TxDone_Busy
;
499 if (Regs::get_TxData_Vaddr(pkt
->get
<uint64_t>())) {
500 panic("vtophys won't work here in newmem.\n");
501 /*Addr vaddr = Regs::get_TxData_Addr(reg64);
502 Addr paddr = vtophys(req->xc, vaddr);
503 DPRINTF(EthernetPIO, "write TxData vnic %d (rxunique %d): "
504 "vaddr=%#x, paddr=%#x\n",
505 index, vnic.txUnique, vaddr, paddr);
507 vnic.TxData = Regs::set_TxData_Addr(vnic.TxData, paddr);*/
509 DPRINTF(EthernetPIO
, "write TxData vnic %d (rxunique %d)\n",
510 index
, vnic
.txUnique
);
513 if (txList
.empty() || txList
.front() != index
)
514 txList
.push_back(index
);
515 if (txEnable
&& txState
== txIdle
&& txList
.front() == index
) {
516 txState
= txFifoBlock
;
526 Device::devIntrPost(uint32_t interrupts
)
528 if ((interrupts
& Regs::Intr_Res
))
529 panic("Cannot set a reserved interrupt");
531 regs
.IntrStatus
|= interrupts
;
533 DPRINTF(EthernetIntr
,
534 "interrupt written to intStatus: intr=%#x status=%#x mask=%#x\n",
535 interrupts
, regs
.IntrStatus
, regs
.IntrMask
);
537 interrupts
= regs
.IntrStatus
& regs
.IntrMask
;
539 // Intr_RxHigh is special, we only signal it if we've emptied the fifo
540 // and then filled it above the high watermark
544 interrupts
&= ~Regs::Intr_RxHigh
;
546 // Intr_TxLow is special, we only signal it if we've filled up the fifo
547 // and then dropped below the low watermark
551 interrupts
&= ~Regs::Intr_TxLow
;
555 if ((interrupts
& Regs::Intr_NoDelay
) == 0)
562 Device::devIntrClear(uint32_t interrupts
)
564 if ((interrupts
& Regs::Intr_Res
))
565 panic("Cannot clear a reserved interrupt");
567 regs
.IntrStatus
&= ~interrupts
;
569 DPRINTF(EthernetIntr
,
570 "interrupt cleared from intStatus: intr=%x status=%x mask=%x\n",
571 interrupts
, regs
.IntrStatus
, regs
.IntrMask
);
573 if (!(regs
.IntrStatus
& regs
.IntrMask
))
578 Device::devIntrChangeMask(uint32_t newmask
)
580 if (regs
.IntrMask
== newmask
)
583 regs
.IntrMask
= newmask
;
585 DPRINTF(EthernetIntr
,
586 "interrupt mask changed: intStatus=%x intMask=%x masked=%x\n",
587 regs
.IntrStatus
, regs
.IntrMask
, regs
.IntrStatus
& regs
.IntrMask
);
589 if (regs
.IntrStatus
& regs
.IntrMask
)
590 cpuIntrPost(curTick
);
596 Base::cpuIntrPost(Tick when
)
598 // If the interrupt you want to post is later than an interrupt
599 // already scheduled, just let it post in the coming one and don't
601 // HOWEVER, must be sure that the scheduled intrTick is in the
602 // future (this was formerly the source of a bug)
604 * @todo this warning should be removed and the intrTick code should
607 assert(when
>= curTick
);
608 assert(intrTick
>= curTick
|| intrTick
== 0);
609 if (!cpuIntrEnable
) {
610 DPRINTF(EthernetIntr
, "interrupts not enabled.\n",
615 if (when
> intrTick
&& intrTick
!= 0) {
616 DPRINTF(EthernetIntr
, "don't need to schedule event...intrTick=%d\n",
622 if (intrTick
< curTick
) {
627 DPRINTF(EthernetIntr
, "going to schedule an interrupt for intrTick=%d\n",
632 intrEvent
= new IntrEvent(this, intrTick
, true);
638 assert(intrTick
== curTick
);
640 // Whether or not there's a pending interrupt, we don't care about
645 // Don't send an interrupt if there's already one
646 if (cpuPendingIntr
) {
647 DPRINTF(EthernetIntr
,
648 "would send an interrupt now, but there's already pending\n");
651 cpuPendingIntr
= true;
653 DPRINTF(EthernetIntr
, "posting interrupt\n");
671 cpuPendingIntr
= false;
673 DPRINTF(EthernetIntr
, "clearing cchip interrupt\n");
678 Base::cpuIntrPending() const
679 { return cpuPendingIntr
; }
682 Device::changeConfig(uint32_t newconf
)
684 uint32_t changed
= regs
.Config
^ newconf
;
688 regs
.Config
= newconf
;
690 if ((changed
& Regs::Config_IntEn
)) {
691 cpuIntrEnable
= regs
.Config
& Regs::Config_IntEn
;
693 if (regs
.IntrStatus
& regs
.IntrMask
)
694 cpuIntrPost(curTick
);
700 if ((changed
& Regs::Config_TxEn
)) {
701 txEnable
= regs
.Config
& Regs::Config_TxEn
;
706 if ((changed
& Regs::Config_RxEn
)) {
707 rxEnable
= regs
.Config
& Regs::Config_RxEn
;
714 Device::command(uint32_t command
)
716 if (command
& Regs::Command_Intr
)
717 devIntrPost(Regs::Intr_Soft
);
719 if (command
& Regs::Command_Reset
)
726 using namespace Regs
;
728 memset(®s
, 0, sizeof(regs
));
731 if (params()->rx_thread
)
732 regs
.Config
|= Config_RxThread
;
733 if (params()->tx_thread
)
734 regs
.Config
|= Config_TxThread
;
736 regs
.Config
|= Config_RSS
;
737 if (params()->zero_copy
)
738 regs
.Config
|= Config_ZeroCopy
;
739 if (params()->delay_copy
)
740 regs
.Config
|= Config_DelayCopy
;
741 if (params()->virtual_addr
)
742 regs
.Config
|= Config_Vaddr
;
744 if (params()->delay_copy
&& params()->zero_copy
)
745 panic("Can't delay copy and zero copy");
747 regs
.IntrMask
= Intr_Soft
| Intr_RxHigh
| Intr_RxPacket
| Intr_TxLow
;
748 regs
.RxMaxCopy
= params()->rx_max_copy
;
749 regs
.TxMaxCopy
= params()->tx_max_copy
;
750 regs
.RxMaxIntr
= params()->rx_max_intr
;
751 regs
.VirtualCount
= params()->virtual_count
;
752 regs
.RxFifoSize
= params()->rx_fifo_size
;
753 regs
.TxFifoSize
= params()->tx_fifo_size
;
754 regs
.RxFifoMark
= params()->rx_fifo_threshold
;
755 regs
.TxFifoMark
= params()->tx_fifo_threshold
;
756 regs
.HwAddr
= params()->hardware_address
;
767 rxFifoPtr
= rxFifo
.end();
773 int size
= virtualRegs
.size();
775 virtualRegs
.resize(size
);
776 for (int i
= 0; i
< size
; ++i
)
777 virtualRegs
[i
].rxPacket
= rxFifo
.end();
783 assert(rxState
== rxCopy
);
784 rxState
= rxCopyDone
;
785 DPRINTF(EthernetDMA
, "end rx dma write paddr=%#x len=%d\n",
786 rxDmaAddr
, rxDmaLen
);
787 DDUMP(EthernetData
, rxDmaData
, rxDmaLen
);
789 // If the transmit state machine has a pending DMA, let it go first
790 if (txState
== txBeginCopy
)
799 VirtualReg
*vnic
= NULL
;
801 DPRINTF(EthernetSM
, "rxKick: rxState=%s (rxFifo.size=%d)\n",
802 RxStateStrings
[rxState
], rxFifo
.size());
804 if (rxKickTick
> curTick
) {
805 DPRINTF(EthernetSM
, "rxKick: exiting, can't run till %d\n",
811 if (rxState
== rxIdle
)
814 if (rxActive
== -1) {
815 if (rxState
!= rxFifoBlock
)
816 panic("no active vnic while in state %s", RxStateStrings
[rxState
]);
818 DPRINTF(EthernetSM
, "processing rxState=%s\n",
819 RxStateStrings
[rxState
]);
821 vnic
= &virtualRegs
[rxActive
];
823 "processing rxState=%s for vnic %d (rxunique %d)\n",
824 RxStateStrings
[rxState
], rxActive
, vnic
->rxUnique
);
829 if (DTRACE(EthernetSM
)) {
830 PacketFifo::iterator end
= rxFifo
.end();
831 int size
= virtualRegs
.size();
832 for (int i
= 0; i
< size
; ++i
) {
833 VirtualReg
*vn
= &virtualRegs
[i
];
834 if (vn
->rxPacket
!= end
&&
835 !Regs::get_RxDone_Busy(vn
->RxDone
)) {
837 "vnic %d (rxunique %d), has outstanding packet %d\n",
839 rxFifo
.countPacketsBefore(vn
->rxPacket
));
844 if (!rxBusy
.empty()) {
845 rxActive
= rxBusy
.front();
847 vnic
= &virtualRegs
[rxActive
];
849 if (vnic
->rxPacket
== rxFifo
.end())
850 panic("continuing vnic without packet\n");
853 "continue processing for vnic %d (rxunique %d)\n",
854 rxActive
, vnic
->rxUnique
);
856 rxState
= rxBeginCopy
;
861 if (rxFifoPtr
== rxFifo
.end()) {
862 DPRINTF(EthernetSM
, "receive waiting for data. Nothing to do.\n");
867 panic("Not idle, but nothing to do!");
869 assert(!rxFifo
.empty());
871 rxActive
= rxList
.front();
873 vnic
= &virtualRegs
[rxActive
];
876 "processing new packet for vnic %d (rxunique %d)\n",
877 rxActive
, vnic
->rxUnique
);
879 // Grab a new packet from the fifo.
880 vnic
->rxPacket
= rxFifoPtr
++;
881 vnic
->rxPacketOffset
= 0;
882 vnic
->rxPacketBytes
= (*vnic
->rxPacket
)->length
;
883 assert(vnic
->rxPacketBytes
);
885 vnic
->rxDoneData
= 0;
886 /* scope for variables */ {
887 IpPtr
ip(*vnic
->rxPacket
);
889 DPRINTF(Ethernet
, "ID is %d\n", ip
->id());
890 vnic
->rxDoneData
|= Regs::RxDone_IpPacket
;
892 if (cksum(ip
) != 0) {
893 DPRINTF(EthernetCksum
, "Rx IP Checksum Error\n");
894 vnic
->rxDoneData
|= Regs::RxDone_IpError
;
900 "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
901 tcp
->sport(), tcp
->dport(), tcp
->seq(),
903 vnic
->rxDoneData
|= Regs::RxDone_TcpPacket
;
905 if (cksum(tcp
) != 0) {
906 DPRINTF(EthernetCksum
, "Rx TCP Checksum Error\n");
907 vnic
->rxDoneData
|= Regs::RxDone_TcpError
;
910 vnic
->rxDoneData
|= Regs::RxDone_UdpPacket
;
912 if (cksum(udp
) != 0) {
913 DPRINTF(EthernetCksum
, "Rx UDP Checksum Error\n");
914 vnic
->rxDoneData
|= Regs::RxDone_UdpError
;
919 rxState
= rxBeginCopy
;
923 if (dmaPending() || getState() != Running
)
926 rxDmaAddr
= params()->platform
->pciToDma(
927 Regs::get_RxData_Addr(vnic
->RxData
));
928 rxDmaLen
= std::min
<int>(Regs::get_RxData_Len(vnic
->RxData
),
929 vnic
->rxPacketBytes
);
930 rxDmaData
= (*vnic
->rxPacket
)->data
+ vnic
->rxPacketOffset
;
932 if (rxDmaAddr
== 1LL) {
933 rxState
= rxCopyDone
;
938 dmaWrite(rxDmaAddr
, rxDmaLen
, &rxDmaEvent
, rxDmaData
);
942 DPRINTF(EthernetSM
, "receive machine still copying\n");
946 vnic
->RxDone
= vnic
->rxDoneData
;
947 vnic
->RxDone
|= Regs::RxDone_Complete
;
949 if (vnic
->rxPacketBytes
== rxDmaLen
) {
950 // Packet is complete. Indicate how many bytes were copied
951 vnic
->RxDone
= Regs::set_RxDone_CopyLen(vnic
->RxDone
, rxDmaLen
);
954 "rxKick: packet complete on vnic %d (rxunique %d)\n",
955 rxActive
, vnic
->rxUnique
);
956 rxFifo
.remove(vnic
->rxPacket
);
957 vnic
->rxPacket
= rxFifo
.end();
959 vnic
->rxPacketBytes
-= rxDmaLen
;
960 vnic
->rxPacketOffset
+= rxDmaLen
;
961 vnic
->RxDone
|= Regs::RxDone_More
;
962 vnic
->RxDone
= Regs::set_RxDone_CopyLen(vnic
->RxDone
,
963 vnic
->rxPacketBytes
);
965 "rxKick: packet not complete on vnic %d (rxunique %d): "
967 rxActive
, vnic
->rxUnique
, vnic
->rxPacketBytes
);
971 rxState
= rxBusy
.empty() && rxList
.empty() ? rxIdle
: rxFifoBlock
;
973 if (rxFifo
.empty()) {
974 devIntrPost(Regs::Intr_RxEmpty
);
978 if (rxFifo
.size() < params()->rx_fifo_low_mark
)
981 if (rxFifo
.size() > params()->rx_fifo_threshold
)
984 devIntrPost(Regs::Intr_RxDMA
);
988 panic("Invalid rxState!");
991 DPRINTF(EthernetSM
, "entering next rxState=%s\n",
992 RxStateStrings
[rxState
]);
998 * @todo do we want to schedule a future kick?
1000 DPRINTF(EthernetSM
, "rx state machine exited rxState=%s\n",
1001 RxStateStrings
[rxState
]);
1007 assert(txState
== txCopy
);
1008 txState
= txCopyDone
;
1009 DPRINTF(EthernetDMA
, "tx dma read paddr=%#x len=%d\n",
1010 txDmaAddr
, txDmaLen
);
1011 DDUMP(EthernetData
, txDmaData
, txDmaLen
);
1013 // If the receive state machine has a pending DMA, let it go first
1014 if (rxState
== rxBeginCopy
)
1023 if (txFifo
.empty()) {
1024 DPRINTF(Ethernet
, "nothing to transmit\n");
1028 uint32_t interrupts
;
1029 EthPacketPtr packet
= txFifo
.front();
1030 if (!interface
->sendPacket(packet
)) {
1031 DPRINTF(Ethernet
, "Packet Transmit: failed txFifo available %d\n",
1038 if (DTRACE(Ethernet
)) {
1041 DPRINTF(Ethernet
, "ID is %d\n", ip
->id());
1045 "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
1046 tcp
->sport(), tcp
->dport(), tcp
->seq(),
1053 DDUMP(EthernetData
, packet
->data
, packet
->length
);
1054 txBytes
+= packet
->length
;
1057 DPRINTF(Ethernet
, "Packet Transmit: successful txFifo Available %d\n",
1060 interrupts
= Regs::Intr_TxPacket
;
1061 if (txFifo
.size() < regs
.TxFifoMark
)
1062 interrupts
|= Regs::Intr_TxLow
;
1063 devIntrPost(interrupts
);
1066 if (!txFifo
.empty() && !txEvent
.scheduled()) {
1067 DPRINTF(Ethernet
, "reschedule transmit\n");
1068 txEvent
.schedule(curTick
+ retryTime
);
1076 DPRINTF(EthernetSM
, "txKick: txState=%s (txFifo.size=%d)\n",
1077 TxStateStrings
[txState
], txFifo
.size());
1079 if (txKickTick
> curTick
) {
1080 DPRINTF(EthernetSM
, "txKick: exiting, can't run till %d\n",
1086 if (txState
== txIdle
)
1089 assert(!txList
.empty());
1090 vnic
= &virtualRegs
[txList
.front()];
1094 assert(Regs::get_TxDone_Busy(vnic
->TxDone
));
1096 // Grab a new packet from the fifo.
1097 txPacket
= new EthPacketData(16384);
1101 if (txFifo
.avail() - txPacket
->length
<
1102 Regs::get_TxData_Len(vnic
->TxData
)) {
1103 DPRINTF(EthernetSM
, "transmit fifo full. Nothing to do.\n");
1107 txState
= txBeginCopy
;
1111 if (dmaPending() || getState() != Running
)
1114 txDmaAddr
= params()->platform
->pciToDma(
1115 Regs::get_TxData_Addr(vnic
->TxData
));
1116 txDmaLen
= Regs::get_TxData_Len(vnic
->TxData
);
1117 txDmaData
= txPacket
->data
+ txPacketOffset
;
1120 dmaRead(txDmaAddr
, txDmaLen
, &txDmaEvent
, txDmaData
);
1124 DPRINTF(EthernetSM
, "transmit machine still copying\n");
1128 vnic
->TxDone
= txDmaLen
| Regs::TxDone_Complete
;
1129 txPacket
->length
+= txDmaLen
;
1130 if ((vnic
->TxData
& Regs::TxData_More
)) {
1131 txPacketOffset
+= txDmaLen
;
1133 devIntrPost(Regs::Intr_TxDMA
);
1137 assert(txPacket
->length
<= txFifo
.avail());
1138 if ((vnic
->TxData
& Regs::TxData_Checksum
)) {
1144 tcp
->sum(cksum(tcp
));
1151 udp
->sum(cksum(udp
));
1161 txFifo
.push(txPacket
);
1162 if (txFifo
.avail() < regs
.TxMaxCopy
) {
1163 devIntrPost(Regs::Intr_TxFull
);
1169 txState
= txList
.empty() ? txIdle
: txFifoBlock
;
1170 devIntrPost(Regs::Intr_TxDMA
);
1174 panic("Invalid txState!");
1177 DPRINTF(EthernetSM
, "entering next txState=%s\n",
1178 TxStateStrings
[txState
]);
1184 * @todo do we want to schedule a future kick?
1186 DPRINTF(EthernetSM
, "tx state machine exited txState=%s\n",
1187 TxStateStrings
[txState
]);
1191 Device::transferDone()
1193 if (txFifo
.empty()) {
1194 DPRINTF(Ethernet
, "transfer complete: txFifo empty...nothing to do\n");
1198 DPRINTF(Ethernet
, "transfer complete: data in txFifo...schedule xmit\n");
1200 txEvent
.reschedule(curTick
+ cycles(1), true);
1204 Device::rxFilter(const EthPacketPtr
&packet
)
1206 if (!Regs::get_Config_Filter(regs
.Config
))
1209 panic("receive filter not implemented\n");
1215 EthHdr
*eth
= packet
->eth();
1216 if (eth
->unicast()) {
1217 // If we're accepting all unicast addresses
1221 // If we make a perfect match
1222 if (acceptPerfect
&& params
->eaddr
== eth
.dst())
1225 if (acceptArp
&& eth
->type() == ETH_TYPE_ARP
)
1228 } else if (eth
->broadcast()) {
1229 // if we're accepting broadcasts
1230 if (acceptBroadcast
)
1233 } else if (eth
->multicast()) {
1234 // if we're accepting all multicasts
1235 if (acceptMulticast
)
1241 DPRINTF(Ethernet
, "rxFilter drop\n");
1242 DDUMP(EthernetData
, packet
->data
, packet
->length
);
1249 Device::recvPacket(EthPacketPtr packet
)
1251 rxBytes
+= packet
->length
;
1254 DPRINTF(Ethernet
, "Receiving packet from wire, rxFifo Available is %d\n",
1258 DPRINTF(Ethernet
, "receive disabled...packet dropped\n");
1262 if (rxFilter(packet
)) {
1263 DPRINTF(Ethernet
, "packet filtered...dropped\n");
1267 if (rxFifo
.size() >= regs
.RxFifoMark
)
1268 devIntrPost(Regs::Intr_RxHigh
);
1270 if (!rxFifo
.push(packet
)) {
1272 "packet will not fit in receive buffer...packet dropped\n");
1276 // If we were at the last element, back up one ot go to the new
1277 // last element of the list.
1278 if (rxFifoPtr
== rxFifo
.end())
1281 devIntrPost(Regs::Intr_RxPacket
);
1289 SimObject::resume();
1291 // During drain we could have left the state machines in a waiting state and
1292 // they wouldn't get out until some other event occured to kick them.
1293 // This way they'll get out immediately
1298 //=====================================================================
1302 Base::serialize(std::ostream
&os
)
1304 // Serialize the PciDev base class
1305 PciDev::serialize(os
);
1307 SERIALIZE_SCALAR(rxEnable
);
1308 SERIALIZE_SCALAR(txEnable
);
1309 SERIALIZE_SCALAR(cpuIntrEnable
);
1312 * Keep track of pending interrupt status.
1314 SERIALIZE_SCALAR(intrTick
);
1315 SERIALIZE_SCALAR(cpuPendingIntr
);
1316 Tick intrEventTick
= 0;
1318 intrEventTick
= intrEvent
->when();
1319 SERIALIZE_SCALAR(intrEventTick
);
1323 Base::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1325 // Unserialize the PciDev base class
1326 PciDev::unserialize(cp
, section
);
1328 UNSERIALIZE_SCALAR(rxEnable
);
1329 UNSERIALIZE_SCALAR(txEnable
);
1330 UNSERIALIZE_SCALAR(cpuIntrEnable
);
1333 * Keep track of pending interrupt status.
1335 UNSERIALIZE_SCALAR(intrTick
);
1336 UNSERIALIZE_SCALAR(cpuPendingIntr
);
1338 UNSERIALIZE_SCALAR(intrEventTick
);
1339 if (intrEventTick
) {
1340 intrEvent
= new IntrEvent(this, intrEventTick
, true);
1345 Device::serialize(std::ostream
&os
)
1349 // Serialize the PciDev base class
1350 Base::serialize(os
);
1352 if (rxState
== rxCopy
)
1353 panic("can't serialize with an in flight dma request rxState=%s",
1354 RxStateStrings
[rxState
]);
1356 if (txState
== txCopy
)
1357 panic("can't serialize with an in flight dma request txState=%s",
1358 TxStateStrings
[txState
]);
1361 * Serialize the device registers
1363 SERIALIZE_SCALAR(regs
.Config
);
1364 SERIALIZE_SCALAR(regs
.IntrStatus
);
1365 SERIALIZE_SCALAR(regs
.IntrMask
);
1366 SERIALIZE_SCALAR(regs
.RxMaxCopy
);
1367 SERIALIZE_SCALAR(regs
.TxMaxCopy
);
1368 SERIALIZE_SCALAR(regs
.RxMaxIntr
);
1369 SERIALIZE_SCALAR(regs
.VirtualCount
);
1370 SERIALIZE_SCALAR(regs
.RxData
);
1371 SERIALIZE_SCALAR(regs
.RxDone
);
1372 SERIALIZE_SCALAR(regs
.TxData
);
1373 SERIALIZE_SCALAR(regs
.TxDone
);
1376 * Serialize the virtual nic state
1378 int virtualRegsSize
= virtualRegs
.size();
1379 SERIALIZE_SCALAR(virtualRegsSize
);
1380 for (int i
= 0; i
< virtualRegsSize
; ++i
) {
1381 VirtualReg
*vnic
= &virtualRegs
[i
];
1383 std::string reg
= csprintf("vnic%d", i
);
1384 paramOut(os
, reg
+ ".RxData", vnic
->RxData
);
1385 paramOut(os
, reg
+ ".RxDone", vnic
->RxDone
);
1386 paramOut(os
, reg
+ ".TxData", vnic
->TxData
);
1387 paramOut(os
, reg
+ ".TxDone", vnic
->TxDone
);
1389 bool rxPacketExists
= vnic
->rxPacket
!= rxFifo
.end();
1390 paramOut(os
, reg
+ ".rxPacketExists", rxPacketExists
);
1391 if (rxPacketExists
) {
1393 PacketFifo::iterator i
= rxFifo
.begin();
1394 while (i
!= vnic
->rxPacket
) {
1395 assert(i
!= rxFifo
.end());
1400 paramOut(os
, reg
+ ".rxPacket", rxPacket
);
1401 paramOut(os
, reg
+ ".rxPacketOffset", vnic
->rxPacketOffset
);
1402 paramOut(os
, reg
+ ".rxPacketBytes", vnic
->rxPacketBytes
);
1404 paramOut(os
, reg
+ ".rxDoneData", vnic
->rxDoneData
);
1407 int rxFifoPtr
= rxFifo
.countPacketsBefore(this->rxFifoPtr
);
1408 SERIALIZE_SCALAR(rxFifoPtr
);
1410 SERIALIZE_SCALAR(rxActive
);
1412 VirtualList::iterator i
, end
;
1413 for (count
= 0, i
= rxList
.begin(), end
= rxList
.end(); i
!= end
; ++i
)
1414 paramOut(os
, csprintf("rxList%d", count
++), *i
);
1415 int rxListSize
= count
;
1416 SERIALIZE_SCALAR(rxListSize
);
1418 for (count
= 0, i
= rxBusy
.begin(), end
= rxBusy
.end(); i
!= end
; ++i
)
1419 paramOut(os
, csprintf("rxBusy%d", count
++), *i
);
1420 int rxBusySize
= count
;
1421 SERIALIZE_SCALAR(rxBusySize
);
1423 for (count
= 0, i
= txList
.begin(), end
= txList
.end(); i
!= end
; ++i
)
1424 paramOut(os
, csprintf("txList%d", count
++), *i
);
1425 int txListSize
= count
;
1426 SERIALIZE_SCALAR(txListSize
);
1429 * Serialize rx state machine
1431 int rxState
= this->rxState
;
1432 SERIALIZE_SCALAR(rxState
);
1433 SERIALIZE_SCALAR(rxEmpty
);
1434 SERIALIZE_SCALAR(rxLow
);
1435 rxFifo
.serialize("rxFifo", os
);
1438 * Serialize tx state machine
1440 int txState
= this->txState
;
1441 SERIALIZE_SCALAR(txState
);
1442 SERIALIZE_SCALAR(txFull
);
1443 txFifo
.serialize("txFifo", os
);
1444 bool txPacketExists
= txPacket
;
1445 SERIALIZE_SCALAR(txPacketExists
);
1446 if (txPacketExists
) {
1447 txPacket
->serialize("txPacket", os
);
1448 SERIALIZE_SCALAR(txPacketOffset
);
1449 SERIALIZE_SCALAR(txPacketBytes
);
1453 * If there's a pending transmit, store the time so we can
1454 * reschedule it later
1456 Tick transmitTick
= txEvent
.scheduled() ? txEvent
.when() - curTick
: 0;
1457 SERIALIZE_SCALAR(transmitTick
);
1461 Device::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1463 // Unserialize the PciDev base class
1464 Base::unserialize(cp
, section
);
1467 * Unserialize the device registers
1469 UNSERIALIZE_SCALAR(regs
.Config
);
1470 UNSERIALIZE_SCALAR(regs
.IntrStatus
);
1471 UNSERIALIZE_SCALAR(regs
.IntrMask
);
1472 UNSERIALIZE_SCALAR(regs
.RxMaxCopy
);
1473 UNSERIALIZE_SCALAR(regs
.TxMaxCopy
);
1474 UNSERIALIZE_SCALAR(regs
.RxMaxIntr
);
1475 UNSERIALIZE_SCALAR(regs
.VirtualCount
);
1476 UNSERIALIZE_SCALAR(regs
.RxData
);
1477 UNSERIALIZE_SCALAR(regs
.RxDone
);
1478 UNSERIALIZE_SCALAR(regs
.TxData
);
1479 UNSERIALIZE_SCALAR(regs
.TxDone
);
1481 UNSERIALIZE_SCALAR(rxActive
);
1484 UNSERIALIZE_SCALAR(rxListSize
);
1486 for (int i
= 0; i
< rxListSize
; ++i
) {
1488 paramIn(cp
, section
, csprintf("rxList%d", i
), value
);
1489 rxList
.push_back(value
);
1493 UNSERIALIZE_SCALAR(rxBusySize
);
1495 for (int i
= 0; i
< rxBusySize
; ++i
) {
1497 paramIn(cp
, section
, csprintf("rxBusy%d", i
), value
);
1498 rxBusy
.push_back(value
);
1502 UNSERIALIZE_SCALAR(txListSize
);
1504 for (int i
= 0; i
< txListSize
; ++i
) {
1506 paramIn(cp
, section
, csprintf("txList%d", i
), value
);
1507 txList
.push_back(value
);
1511 * Unserialize rx state machine
1514 UNSERIALIZE_SCALAR(rxState
);
1515 UNSERIALIZE_SCALAR(rxEmpty
);
1516 UNSERIALIZE_SCALAR(rxLow
);
1517 this->rxState
= (RxState
) rxState
;
1518 rxFifo
.unserialize("rxFifo", cp
, section
);
1521 UNSERIALIZE_SCALAR(rxFifoPtr
);
1522 this->rxFifoPtr
= rxFifo
.begin();
1523 for (int i
= 0; i
< rxFifoPtr
; ++i
)
1527 * Unserialize tx state machine
1530 UNSERIALIZE_SCALAR(txState
);
1531 UNSERIALIZE_SCALAR(txFull
);
1532 this->txState
= (TxState
) txState
;
1533 txFifo
.unserialize("txFifo", cp
, section
);
1534 bool txPacketExists
;
1535 UNSERIALIZE_SCALAR(txPacketExists
);
1537 if (txPacketExists
) {
1538 txPacket
= new EthPacketData(16384);
1539 txPacket
->unserialize("txPacket", cp
, section
);
1540 UNSERIALIZE_SCALAR(txPacketOffset
);
1541 UNSERIALIZE_SCALAR(txPacketBytes
);
1545 * unserialize the virtual nic registers/state
1547 * this must be done after the unserialization of the rxFifo
1548 * because the packet iterators depend on the fifo being populated
1550 int virtualRegsSize
;
1551 UNSERIALIZE_SCALAR(virtualRegsSize
);
1552 virtualRegs
.clear();
1553 virtualRegs
.resize(virtualRegsSize
);
1554 for (int i
= 0; i
< virtualRegsSize
; ++i
) {
1555 VirtualReg
*vnic
= &virtualRegs
[i
];
1556 std::string reg
= csprintf("vnic%d", i
);
1558 paramIn(cp
, section
, reg
+ ".RxData", vnic
->RxData
);
1559 paramIn(cp
, section
, reg
+ ".RxDone", vnic
->RxDone
);
1560 paramIn(cp
, section
, reg
+ ".TxData", vnic
->TxData
);
1561 paramIn(cp
, section
, reg
+ ".TxDone", vnic
->TxDone
);
1563 vnic
->rxUnique
= rxUnique
++;
1564 vnic
->txUnique
= txUnique
++;
1566 bool rxPacketExists
;
1567 paramIn(cp
, section
, reg
+ ".rxPacketExists", rxPacketExists
);
1568 if (rxPacketExists
) {
1570 paramIn(cp
, section
, reg
+ ".rxPacket", rxPacket
);
1571 vnic
->rxPacket
= rxFifo
.begin();
1575 paramIn(cp
, section
, reg
+ ".rxPacketOffset",
1576 vnic
->rxPacketOffset
);
1577 paramIn(cp
, section
, reg
+ ".rxPacketBytes", vnic
->rxPacketBytes
);
1579 vnic
->rxPacket
= rxFifo
.end();
1581 paramIn(cp
, section
, reg
+ ".rxDoneData", vnic
->rxDoneData
);
1585 * If there's a pending transmit, reschedule it now
1588 UNSERIALIZE_SCALAR(transmitTick
);
1590 txEvent
.schedule(curTick
+ transmitTick
);
1592 pioPort
->sendStatusChange(Port::RangeChange
);
1596 /* namespace Sinic */ }
1599 SinicIntParams::create()
1601 using namespace Sinic
;
1603 Interface
*dev_int
= new Interface(name
, device
);
1606 dev_int
->setPeer(peer
);
1607 peer
->setPeer(dev_int
);
1614 SinicParams::create()
1616 return new Sinic::Device(this);