src/dev/sinic.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __DEV_SINIC_HH__
  30 #define __DEV_SINIC_HH__
  31
  32 #include "base/inet.hh"
  33 #include "base/statistics.hh"
  34 #include "dev/etherint.hh"
  35 #include "dev/etherpkt.hh"
  36 #include "dev/io_device.hh"
  37 #include "dev/pcidev.hh"
  38 #include "dev/pktfifo.hh"
  39 #include "dev/sinicreg.hh"
  40 #include "sim/eventq.hh"
  41
  42 namespace Sinic {
  43
  44 class Interface;
  45 class Base : public PciDev
  46 {
  47   protected:
  48     bool rxEnable;
  49     bool txEnable;
  50     Tick clock;
  51     inline Tick cycles(int numCycles) const { return numCycles * clock; }
  52
  53   protected:
  54     Tick intrDelay;
  55     Tick intrTick;
  56     bool cpuIntrEnable;
  57     bool cpuPendingIntr;
  58     void cpuIntrPost(Tick when);
  59     void cpuInterrupt();
  60     void cpuIntrClear();
  61
  62     typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
  63     friend void IntrEvent::process();
  64     IntrEvent *intrEvent;
  65     Interface *interface;
  66
  67     bool cpuIntrPending() const;
  68     void cpuIntrAck() { cpuIntrClear(); }
  69
  70 /**
  71  * Serialization stuff
  72  */
  73   public:
  74     virtual void serialize(std::ostream &os);
  75     virtual void unserialize(Checkpoint *cp, const std::string &section);
  76
  77 /**
  78  * Construction/Destruction/Parameters
  79  */
  80   public:
  81     struct Params : public PciDev::Params
  82     {
  83         Tick clock;
  84         Tick intr_delay;
  85     };
  86
  87     Base(Params *p);
  88 };
  89
  90 class Device : public Base
  91 {
  92   protected:
  93     /** Receive State Machine States */
  94     enum RxState {
  95         rxIdle,
  96         rxFifoBlock,
  97         rxBeginCopy,
  98         rxCopy,
  99         rxCopyDone
 100     };
 101
 102     /** Transmit State Machine states */
 103     enum TxState {
 104         txIdle,
 105         txFifoBlock,
 106         txBeginCopy,
 107         txCopy,
 108         txCopyDone
 109     };
 110
 111     /** device register file */
 112     struct {
 113         uint32_t Config;       // 0x00
 114         uint32_t Command;      // 0x04
 115         uint32_t IntrStatus;   // 0x08
 116         uint32_t IntrMask;     // 0x0c
 117         uint32_t RxMaxCopy;    // 0x10
 118         uint32_t TxMaxCopy;    // 0x14
 119         uint32_t RxMaxIntr;    // 0x18
 120         uint32_t VirtualCount; // 0x1c
 121         uint32_t RxFifoSize;   // 0x20
 122         uint32_t TxFifoSize;   // 0x24
 123         uint32_t RxFifoMark;   // 0x28
 124         uint32_t TxFifoMark;   // 0x2c
 125         uint64_t RxData;       // 0x30
 126         uint64_t RxDone;       // 0x38
 127         uint64_t RxWait;       // 0x40
 128         uint64_t TxData;       // 0x48
 129         uint64_t TxDone;       // 0x50
 130         uint64_t TxWait;       // 0x58
 131         uint64_t HwAddr;       // 0x60
 132     } regs;
 133
 134     struct VirtualReg {
 135         uint64_t RxData;
 136         uint64_t RxDone;
 137         uint64_t TxData;
 138         uint64_t TxDone;
 139
 140         PacketFifo::iterator rxPacket;
 141         int rxPacketOffset;
 142         int rxPacketBytes;
 143         uint64_t rxDoneData;
 144
 145         Counter rxUnique;
 146         Counter txUnique;
 147
 148         VirtualReg()
 149             : RxData(0), RxDone(0), TxData(0), TxDone(0),
 150               rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
 151         { }
 152     };
 153     typedef std::vector<VirtualReg> VirtualRegs;
 154     typedef std::list<int> VirtualList;
 155     Counter rxUnique;
 156     Counter txUnique;
 157     VirtualRegs virtualRegs;
 158     VirtualList rxList;
 159     VirtualList rxBusy;
 160     int rxActive;
 161     VirtualList txList;
 162
 163     uint8_t  &regData8(Addr daddr) { return *((uint8_t *)&regs + daddr); }
 164     uint32_t &regData32(Addr daddr) { return *(uint32_t *)&regData8(daddr); }
 165     uint64_t &regData64(Addr daddr) { return *(uint64_t *)&regData8(daddr); }
 166
 167   protected:
 168     RxState rxState;
 169     PacketFifo rxFifo;
 170     PacketFifo::iterator rxFifoPtr;
 171     bool rxEmpty;
 172     bool rxLow;
 173     Addr rxDmaAddr;
 174     uint8_t *rxDmaData;
 175     int rxDmaLen;
 176
 177     TxState txState;
 178     PacketFifo txFifo;
 179     bool txFull;
 180     EthPacketPtr txPacket;
 181     int txPacketOffset;
 182     int txPacketBytes;
 183     Addr txDmaAddr;
 184     uint8_t *txDmaData;
 185     int txDmaLen;
 186
 187   protected:
 188     void reset();
 189
 190     void rxKick();
 191     Tick rxKickTick;
 192     typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
 193     friend void RxKickEvent::process();
 194
 195     void txKick();
 196     Tick txKickTick;
 197     typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
 198     friend void TxKickEvent::process();
 199
 200     /**
 201      * Retransmit event
 202      */
 203     void transmit();
 204     void txEventTransmit()
 205     {
 206         transmit();
 207         if (txState == txFifoBlock)
 208             txKick();
 209     }
 210     typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
 211     friend void TxEvent::process();
 212     TxEvent txEvent;
 213
 214     void txDump() const;
 215     void rxDump() const;
 216
 217     /**
 218      * receive address filter
 219      */
 220     bool rxFilter(const EthPacketPtr &packet);
 221
 222 /**
 223  * device configuration
 224  */
 225     void changeConfig(uint32_t newconfig);
 226     void command(uint32_t command);
 227
 228 /**
 229  * device ethernet interface
 230  */
 231   public:
 232     bool recvPacket(EthPacketPtr packet);
 233     void transferDone();
 234     void setInterface(Interface *i) { assert(!interface); interface = i; }
 235
 236 /**
 237  * DMA parameters
 238  */
 239   protected:
 240     void rxDmaDone();
 241     friend class EventWrapper<Device, &Device::rxDmaDone>;
 242     EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
 243
 244     void txDmaDone();
 245     friend class EventWrapper<Device, &Device::txDmaDone>;
 246     EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
 247
 248     Tick dmaReadDelay;
 249     Tick dmaReadFactor;
 250     Tick dmaWriteDelay;
 251     Tick dmaWriteFactor;
 252
 253 /**
 254  * Interrupt management
 255  */
 256   protected:
 257     void devIntrPost(uint32_t interrupts);
 258     void devIntrClear(uint32_t interrupts = Regs::Intr_All);
 259     void devIntrChangeMask(uint32_t newmask);
 260
 261 /**
 262  * Memory Interface
 263  */
 264   public:
 265     virtual Tick read(Packet *pkt);
 266     virtual Tick write(Packet *pkt);
 267
 268     void prepareIO(int cpu, int index);
 269     void prepareRead(int cpu, int index);
 270     void prepareWrite(int cpu, int index);
 271  //   Fault iprRead(Addr daddr, int cpu, uint64_t &result);
 272
 273 /**
 274  * Statistics
 275  */
 276   private:
 277     Stats::Scalar<> rxBytes;
 278     Stats::Formula  rxBandwidth;
 279     Stats::Scalar<> rxPackets;
 280     Stats::Formula  rxPacketRate;
 281     Stats::Scalar<> rxIpPackets;
 282     Stats::Scalar<> rxTcpPackets;
 283     Stats::Scalar<> rxUdpPackets;
 284     Stats::Scalar<> rxIpChecksums;
 285     Stats::Scalar<> rxTcpChecksums;
 286     Stats::Scalar<> rxUdpChecksums;
 287
 288     Stats::Scalar<> txBytes;
 289     Stats::Formula  txBandwidth;
 290     Stats::Formula totBandwidth;
 291     Stats::Formula totPackets;
 292     Stats::Formula totBytes;
 293     Stats::Formula totPacketRate;
 294     Stats::Scalar<> txPackets;
 295     Stats::Formula  txPacketRate;
 296     Stats::Scalar<> txIpPackets;
 297     Stats::Scalar<> txTcpPackets;
 298     Stats::Scalar<> txUdpPackets;
 299     Stats::Scalar<> txIpChecksums;
 300     Stats::Scalar<> txTcpChecksums;
 301     Stats::Scalar<> txUdpChecksums;
 302
 303   public:
 304     virtual void regStats();
 305
 306 /**
 307  * Serialization stuff
 308  */
 309   public:
 310     virtual void serialize(std::ostream &os);
 311     virtual void unserialize(Checkpoint *cp, const std::string &section);
 312
 313 /**
 314  * Construction/Destruction/Parameters
 315  */
 316   public:
 317     struct Params : public Base::Params
 318     {
 319         Tick tx_delay;
 320         Tick rx_delay;
 321         bool rx_filter;
 322         Net::EthAddr eaddr;
 323         uint32_t rx_max_copy;
 324         uint32_t tx_max_copy;
 325         uint32_t rx_max_intr;
 326         uint32_t rx_fifo_size;
 327         uint32_t tx_fifo_size;
 328         uint32_t rx_fifo_threshold;
 329         uint32_t rx_fifo_low_mark;
 330         uint32_t tx_fifo_high_mark;
 331         uint32_t tx_fifo_threshold;
 332         Tick dma_read_delay;
 333         Tick dma_read_factor;
 334         Tick dma_write_delay;
 335         Tick dma_write_factor;
 336         bool rx_thread;
 337         bool tx_thread;
 338         bool rss;
 339         uint32_t virtual_count;
 340         bool zero_copy;
 341         bool delay_copy;
 342         bool virtual_addr;
 343     };
 344
 345   protected:
 346     const Params *params() const { return (const Params *)_params; }
 347
 348   public:
 349     Device(Params *params);
 350     ~Device();
 351 };
 352
 353 /*
 354  * Ethernet Interface for an Ethernet Device
 355  */
 356 class Interface : public EtherInt
 357 {
 358   private:
 359     Device *dev;
 360
 361   public:
 362     Interface(const std::string &name, Device *d)
 363         : EtherInt(name), dev(d) { dev->setInterface(this); }
 364
 365     virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
 366     virtual void sendDone() { dev->transferDone(); }
 367 };
 368
 369 /* namespace Sinic */ }
 370
 371 #endif // __DEV_SINIC_HH__