2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #ifndef __DEV_SINIC_HH__
30 #define __DEV_SINIC_HH__
32 #include "base/inet.hh"
33 #include "base/statistics.hh"
34 #include "dev/etherint.hh"
35 #include "dev/etherpkt.hh"
36 #include "dev/io_device.hh"
37 #include "dev/pcidev.hh"
38 #include "dev/pktfifo.hh"
39 #include "dev/sinicreg.hh"
40 #include "sim/eventq.hh"
45 class Base : public PciDev
51 inline Tick cycles(int numCycles) const { return numCycles * clock; }
58 void cpuIntrPost(Tick when);
62 typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
63 friend void IntrEvent::process();
67 bool cpuIntrPending() const;
68 void cpuIntrAck() { cpuIntrClear(); }
74 virtual void serialize(std::ostream &os);
75 virtual void unserialize(Checkpoint *cp, const std::string §ion);
78 * Construction/Destruction/Parameters
81 struct Params : public PciDev::Params
90 class Device : public Base
93 /** Receive State Machine States */
102 /** Transmit State Machine states */
111 /** device register file */
113 uint32_t Config; // 0x00
114 uint32_t Command; // 0x04
115 uint32_t IntrStatus; // 0x08
116 uint32_t IntrMask; // 0x0c
117 uint32_t RxMaxCopy; // 0x10
118 uint32_t TxMaxCopy; // 0x14
119 uint32_t RxMaxIntr; // 0x18
120 uint32_t VirtualCount; // 0x1c
121 uint32_t RxFifoSize; // 0x20
122 uint32_t TxFifoSize; // 0x24
123 uint32_t RxFifoMark; // 0x28
124 uint32_t TxFifoMark; // 0x2c
125 uint64_t RxData; // 0x30
126 uint64_t RxDone; // 0x38
127 uint64_t RxWait; // 0x40
128 uint64_t TxData; // 0x48
129 uint64_t TxDone; // 0x50
130 uint64_t TxWait; // 0x58
131 uint64_t HwAddr; // 0x60
140 PacketFifo::iterator rxPacket;
149 : RxData(0), RxDone(0), TxData(0), TxDone(0),
150 rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
153 typedef std::vector<VirtualReg> VirtualRegs;
154 typedef std::list<int> VirtualList;
157 VirtualRegs virtualRegs;
163 uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); }
164 uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); }
165 uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); }
170 PacketFifo::iterator rxFifoPtr;
180 EthPacketPtr txPacket;
192 typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
193 friend void RxKickEvent::process();
197 typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
198 friend void TxKickEvent::process();
204 void txEventTransmit()
207 if (txState == txFifoBlock)
210 typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
211 friend void TxEvent::process();
218 * receive address filter
220 bool rxFilter(const EthPacketPtr &packet);
223 * device configuration
225 void changeConfig(uint32_t newconfig);
226 void command(uint32_t command);
229 * device ethernet interface
232 bool recvPacket(EthPacketPtr packet);
234 void setInterface(Interface *i) { assert(!interface); interface = i; }
241 friend class EventWrapper<Device, &Device::rxDmaDone>;
242 EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
245 friend class EventWrapper<Device, &Device::txDmaDone>;
246 EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
254 * Interrupt management
257 void devIntrPost(uint32_t interrupts);
258 void devIntrClear(uint32_t interrupts = Regs::Intr_All);
259 void devIntrChangeMask(uint32_t newmask);
265 virtual Tick read(Packet *pkt);
266 virtual Tick write(Packet *pkt);
268 void prepareIO(int cpu, int index);
269 void prepareRead(int cpu, int index);
270 void prepareWrite(int cpu, int index);
271 // Fault iprRead(Addr daddr, int cpu, uint64_t &result);
277 Stats::Scalar<> rxBytes;
278 Stats::Formula rxBandwidth;
279 Stats::Scalar<> rxPackets;
280 Stats::Formula rxPacketRate;
281 Stats::Scalar<> rxIpPackets;
282 Stats::Scalar<> rxTcpPackets;
283 Stats::Scalar<> rxUdpPackets;
284 Stats::Scalar<> rxIpChecksums;
285 Stats::Scalar<> rxTcpChecksums;
286 Stats::Scalar<> rxUdpChecksums;
288 Stats::Scalar<> txBytes;
289 Stats::Formula txBandwidth;
290 Stats::Formula totBandwidth;
291 Stats::Formula totPackets;
292 Stats::Formula totBytes;
293 Stats::Formula totPacketRate;
294 Stats::Scalar<> txPackets;
295 Stats::Formula txPacketRate;
296 Stats::Scalar<> txIpPackets;
297 Stats::Scalar<> txTcpPackets;
298 Stats::Scalar<> txUdpPackets;
299 Stats::Scalar<> txIpChecksums;
300 Stats::Scalar<> txTcpChecksums;
301 Stats::Scalar<> txUdpChecksums;
304 virtual void regStats();
307 * Serialization stuff
310 virtual void serialize(std::ostream &os);
311 virtual void unserialize(Checkpoint *cp, const std::string §ion);
314 * Construction/Destruction/Parameters
317 struct Params : public Base::Params
323 uint32_t rx_max_copy;
324 uint32_t tx_max_copy;
325 uint32_t rx_max_intr;
326 uint32_t rx_fifo_size;
327 uint32_t tx_fifo_size;
328 uint32_t rx_fifo_threshold;
329 uint32_t rx_fifo_low_mark;
330 uint32_t tx_fifo_high_mark;
331 uint32_t tx_fifo_threshold;
333 Tick dma_read_factor;
334 Tick dma_write_delay;
335 Tick dma_write_factor;
339 uint32_t virtual_count;
346 const Params *params() const { return (const Params *)_params; }
349 Device(Params *params);
354 * Ethernet Interface for an Ethernet Device
356 class Interface : public EtherInt
362 Interface(const std::string &name, Device *d)
363 : EtherInt(name), dev(d) { dev->setInterface(this); }
365 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
366 virtual void sendDone() { dev->transferDone(); }
369 /* namespace Sinic */ }
371 #endif // __DEV_SINIC_HH__