2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
31 #ifndef __DEV_SINIC_HH__
32 #define __DEV_SINIC_HH__
34 #include "base/inet.hh"
35 #include "base/statistics.hh"
36 #include "dev/etherint.hh"
37 #include "dev/etherpkt.hh"
38 #include "dev/io_device.hh"
39 #include "dev/pcidev.hh"
40 #include "dev/pktfifo.hh"
41 #include "dev/sinicreg.hh"
42 #include "sim/eventq.hh"
47 class Base : public PciDev
53 inline Tick cycles(int numCycles) const { return numCycles * clock; }
60 void cpuIntrPost(Tick when);
64 typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
65 friend void IntrEvent::process();
69 bool cpuIntrPending() const;
70 void cpuIntrAck() { cpuIntrClear(); }
76 virtual void serialize(std::ostream &os);
77 virtual void unserialize(Checkpoint *cp, const std::string §ion);
80 * Construction/Destruction/Parameters
83 struct Params : public PciDev::Params
92 class Device : public Base
95 /** Receive State Machine States */
104 /** Transmit State Machine states */
113 /** device register file */
115 uint32_t Config; // 0x00
116 uint32_t Command; // 0x04
117 uint32_t IntrStatus; // 0x08
118 uint32_t IntrMask; // 0x0c
119 uint32_t RxMaxCopy; // 0x10
120 uint32_t TxMaxCopy; // 0x14
121 uint32_t RxMaxIntr; // 0x18
122 uint32_t VirtualCount; // 0x1c
123 uint32_t RxFifoSize; // 0x20
124 uint32_t TxFifoSize; // 0x24
125 uint32_t RxFifoMark; // 0x28
126 uint32_t TxFifoMark; // 0x2c
127 uint64_t RxData; // 0x30
128 uint64_t RxDone; // 0x38
129 uint64_t RxWait; // 0x40
130 uint64_t TxData; // 0x48
131 uint64_t TxDone; // 0x50
132 uint64_t TxWait; // 0x58
133 uint64_t HwAddr; // 0x60
142 PacketFifo::iterator rxPacket;
151 : RxData(0), RxDone(0), TxData(0), TxDone(0),
152 rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
155 typedef std::vector<VirtualReg> VirtualRegs;
156 typedef std::list<int> VirtualList;
159 VirtualRegs virtualRegs;
165 uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); }
166 uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); }
167 uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); }
172 PacketFifo::iterator rxFifoPtr;
182 EthPacketPtr txPacket;
194 typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
195 friend void RxKickEvent::process();
199 typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
200 friend void TxKickEvent::process();
206 void txEventTransmit()
209 if (txState == txFifoBlock)
212 typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
213 friend void TxEvent::process();
220 * receive address filter
222 bool rxFilter(const EthPacketPtr &packet);
225 * device configuration
227 void changeConfig(uint32_t newconfig);
228 void command(uint32_t command);
231 * device ethernet interface
234 bool recvPacket(EthPacketPtr packet);
236 void setInterface(Interface *i) { assert(!interface); interface = i; }
243 friend class EventWrapper<Device, &Device::rxDmaDone>;
244 EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
247 friend class EventWrapper<Device, &Device::txDmaDone>;
248 EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
256 * Interrupt management
259 void devIntrPost(uint32_t interrupts);
260 void devIntrClear(uint32_t interrupts = Regs::Intr_All);
261 void devIntrChangeMask(uint32_t newmask);
267 virtual Tick read(PacketPtr pkt);
268 virtual Tick write(PacketPtr pkt);
269 virtual void resume();
271 void prepareIO(int cpu, int index);
272 void prepareRead(int cpu, int index);
273 void prepareWrite(int cpu, int index);
274 // Fault iprRead(Addr daddr, int cpu, uint64_t &result);
280 Stats::Scalar<> rxBytes;
281 Stats::Formula rxBandwidth;
282 Stats::Scalar<> rxPackets;
283 Stats::Formula rxPacketRate;
284 Stats::Scalar<> rxIpPackets;
285 Stats::Scalar<> rxTcpPackets;
286 Stats::Scalar<> rxUdpPackets;
287 Stats::Scalar<> rxIpChecksums;
288 Stats::Scalar<> rxTcpChecksums;
289 Stats::Scalar<> rxUdpChecksums;
291 Stats::Scalar<> txBytes;
292 Stats::Formula txBandwidth;
293 Stats::Formula totBandwidth;
294 Stats::Formula totPackets;
295 Stats::Formula totBytes;
296 Stats::Formula totPacketRate;
297 Stats::Scalar<> txPackets;
298 Stats::Formula txPacketRate;
299 Stats::Scalar<> txIpPackets;
300 Stats::Scalar<> txTcpPackets;
301 Stats::Scalar<> txUdpPackets;
302 Stats::Scalar<> txIpChecksums;
303 Stats::Scalar<> txTcpChecksums;
304 Stats::Scalar<> txUdpChecksums;
307 virtual void regStats();
310 * Serialization stuff
313 virtual void serialize(std::ostream &os);
314 virtual void unserialize(Checkpoint *cp, const std::string §ion);
317 * Construction/Destruction/Parameters
320 struct Params : public Base::Params
326 uint32_t rx_max_copy;
327 uint32_t tx_max_copy;
328 uint32_t rx_max_intr;
329 uint32_t rx_fifo_size;
330 uint32_t tx_fifo_size;
331 uint32_t rx_fifo_threshold;
332 uint32_t rx_fifo_low_mark;
333 uint32_t tx_fifo_high_mark;
334 uint32_t tx_fifo_threshold;
336 Tick dma_read_factor;
337 Tick dma_write_delay;
338 Tick dma_write_factor;
342 uint32_t virtual_count;
349 const Params *params() const { return (const Params *)_params; }
352 Device(Params *params);
357 * Ethernet Interface for an Ethernet Device
359 class Interface : public EtherInt
365 Interface(const std::string &name, Device *d)
366 : EtherInt(name), dev(d) { dev->setInterface(this); }
368 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
369 virtual void sendDone() { dev->transferDone(); }
372 /* namespace Sinic */ }
374 #endif // __DEV_SINIC_HH__