src/dev/sparc/T1000.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26
  27 from m5.params import *
  28 from m5.proxy import *
  29
  30 from m5.objects.Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
  31 from m5.objects.Platform import Platform
  32 from m5.objects.Terminal import Terminal
  33 from m5.objects.Uart import Uart8250
  34
  35
  36 class MmDisk(BasicPioDevice):
  37     type = 'MmDisk'
  38     cxx_header = "dev/sparc/mm_disk.hh"
  39     image = Param.DiskImage("Disk Image")
  40     pio_addr = 0x1F40000000
  41
  42 class DumbTOD(BasicPioDevice):
  43     type = 'DumbTOD'
  44     cxx_header = "dev/sparc/dtod.hh"
  45     time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
  46     pio_addr = 0xfff0c1fff8
  47
  48 class Iob(PioDevice):
  49     type = 'Iob'
  50     cxx_header = "dev/sparc/iob.hh"
  51     platform = Param.Platform(Parent.any, "Platform this device is part of.")
  52     pio_latency = Param.Latency('1ns', "Programed IO latency")
  53
  54
  55 class T1000(Platform):
  56     type = 'T1000'
  57     cxx_header = "dev/sparc/t1000.hh"
  58     system = Param.System(Parent.any, "system")
  59
  60     fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
  61             #warn_access="Accessing Clock Unit -- Unimplemented!")
  62
  63     fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
  64             ret_data64=0x0000000000000000, update_data=False)
  65             #warn_access="Accessing Memory Banks -- Unimplemented!")
  66
  67     fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
  68             #warn_access="Accessing JBI -- Unimplemented!")
  69
  70     fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
  71             ret_data64=0x0000000000000001, update_data=True)
  72             #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
  73
  74     fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
  75             ret_data64=0x0000000000000001, update_data=True)
  76             #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
  77
  78     fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
  79             ret_data64=0x0000000000000001, update_data=True)
  80             #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
  81
  82     fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
  83             ret_data64=0x0000000000000001, update_data=True)
  84             #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
  85
  86     fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
  87             ret_data64=0x0000000000000000, update_data=True)
  88             #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
  89
  90     fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
  91             ret_data64=0x0000000000000000, update_data=True)
  92             #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
  93
  94     fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
  95             ret_data64=0x0000000000000000, update_data=True)
  96             #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
  97
  98     fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
  99             ret_data64=0x0000000000000000, update_data=True)
 100             #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
 101
 102     fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
 103             #warn_access="Accessing SSI -- Unimplemented!")
 104
 105     hterm = Terminal()
 106     hvuart = Uart8250(pio_addr=0xfff0c2c000)
 107     htod = DumbTOD()
 108
 109     pterm = Terminal()
 110     puart0 = Uart8250(pio_addr=0x1f10000000)
 111
 112     iob = Iob()
 113     # Attach I/O devices that are on chip
 114     def attachOnChipIO(self, bus):
 115         self.iob.pio = bus.mem_side_ports
 116         self.htod.pio = bus.mem_side_ports
 117
 118
 119     # Attach I/O devices to specified bus object.  Can't do this
 120     # earlier, since the bus object itself is typically defined at the
 121     # System level.
 122     def attachIO(self, bus):
 123         self.hvuart.device = self.hterm
 124         self.puart0.device = self.pterm
 125         self.fake_clk.pio = bus.mem_side_ports
 126         self.fake_membnks.pio = bus.mem_side_ports
 127         self.fake_l2_1.pio = bus.mem_side_ports
 128         self.fake_l2_2.pio = bus.mem_side_ports
 129         self.fake_l2_3.pio = bus.mem_side_ports
 130         self.fake_l2_4.pio = bus.mem_side_ports
 131         self.fake_l2esr_1.pio = bus.mem_side_ports
 132         self.fake_l2esr_2.pio = bus.mem_side_ports
 133         self.fake_l2esr_3.pio = bus.mem_side_ports
 134         self.fake_l2esr_4.pio = bus.mem_side_ports
 135         self.fake_ssi.pio = bus.mem_side_ports
 136         self.fake_jbi.pio = bus.mem_side_ports
 137         self.puart0.pio = bus.mem_side_ports
 138         self.hvuart.pio = bus.mem_side_ports