src/dev/sparc/iob.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /** @file
  32  * This device implements the niagara I/O Bridge chip. The device manages
  33  * internal (ipi) and external (serial, pci via jbus).
  34  */
  35
  36 #ifndef __DEV_SPARC_IOB_HH__
  37 #define __DEV_SPARC_IOB_HH__
  38
  39 #include "dev/io_device.hh"
  40 #include "params/Iob.hh"
  41
  42 class IntrControl;
  43
  44 const int  MaxNiagaraProcs = 32;
  45 // IOB Managment Addresses
  46 const Addr IntManAddr       = 0x0000;
  47 const Addr IntManSize       = 0x0020;
  48 const Addr IntCtlAddr       = 0x0400;
  49 const Addr IntCtlSize       = 0x0020;
  50 const Addr JIntVecAddr      = 0x0A00;
  51 const Addr IntVecDisAddr    = 0x0800;
  52 const Addr IntVecDisSize    = 0x0100;
  53
  54
  55 // IOB Control Addresses
  56 const Addr JIntData0Addr   = 0x0400;
  57 const Addr JIntData1Addr   = 0x0500;
  58 const Addr JIntDataA0Addr  = 0x0600;
  59 const Addr JIntDataA1Addr  = 0x0700;
  60 const Addr JIntBusyAddr    = 0x0900;
  61 const Addr JIntBusySize    = 0x0100;
  62 const Addr JIntABusyAddr   = 0x0B00;
  63
  64
  65 // IOB Masks
  66 const uint64_t IntManMask   = 0x01F3F;
  67 const uint64_t IntCtlMask   = 0x00006;
  68 const uint64_t JIntVecMask  = 0x0003F;
  69 const uint64_t IntVecDis    = 0x31F3F;
  70 const uint64_t JIntBusyMask = 0x0003F;
  71
  72
  73 class Iob : public PioDevice
  74 {
  75   private:
  76     IntrControl *ic;
  77     Addr iobManAddr;
  78     Addr iobManSize;
  79     Addr iobJBusAddr;
  80     Addr iobJBusSize;
  81     Tick pioDelay;
  82
  83     enum DeviceId {
  84         Interal = 0,
  85         Error = 1,
  86         SSI = 2,
  87         Reserved = 3,
  88         NumDeviceIds
  89     };
  90
  91     struct IntMan {
  92         int cpu;
  93         int vector;
  94     };
  95
  96     struct IntCtl {
  97         bool mask;
  98         bool pend;
  99     };
 100
 101     struct IntBusy {
 102         bool busy;
 103         int source;
 104     };
 105
 106     enum Type {
 107         Interrupt,
 108         Reset,
 109         Idle,
 110         Resume
 111     };
 112
 113     IntMan intMan[NumDeviceIds];
 114     IntCtl intCtl[NumDeviceIds];
 115     uint64_t jIntVec;
 116     uint64_t jBusData0[MaxNiagaraProcs];
 117     uint64_t jBusData1[MaxNiagaraProcs];
 118     IntBusy jIntBusy[MaxNiagaraProcs];
 119
 120     void writeIob(PacketPtr pkt);
 121     void writeJBus(PacketPtr pkt);
 122     void readIob(PacketPtr pkt);
 123     void readJBus(PacketPtr pkt);
 124
 125   public:
 126     typedef IobParams Params;
 127     Iob(const Params *p);
 128
 129     const Params *
 130     params() const
 131     {
 132         return dynamic_cast<const Params *>(_params);
 133     }
 134
 135     Tick read(PacketPtr pkt) override;
 136     Tick write(PacketPtr pkt) override;
 137     void generateIpi(Type type, int cpu_id, int vector);
 138     void receiveDeviceInterrupt(DeviceId devid);
 139     bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
 140                               uint64_t d1);
 141
 142     AddrRangeList getAddrRanges() const override;
 143
 144     void serialize(CheckpointOut &cp) const override;
 145     void unserialize(CheckpointIn &cp) override;
 146 };
 147
 148 #endif //__DEV_SPARC_IOB_HH__
 149