src/dev/sparc/t1000.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /** @file
  32  * Implementation of T1000 platform.
  33  */
  34
  35 #include <deque>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "cpu/intr_control.hh"
  40 #include "dev/simconsole.hh"
  41 #include "dev/sparc/t1000.hh"
  42 #include "sim/builder.hh"
  43 #include "sim/system.hh"
  44
  45 using namespace std;
  46 //Should this be AlphaISA?
  47 using namespace TheISA;
  48
  49 T1000::T1000(const string &name, System *s, IntrControl *ic)
  50     : Platform(name, ic), system(s)
  51 {
  52     // set the back pointer from the system to myself
  53     system->platform = this;
  54 }
  55
  56 Tick
  57 T1000::intrFrequency()
  58 {
  59     panic("Need implementation\n");
  60 }
  61
  62 void
  63 T1000::postConsoleInt()
  64 {
  65     warn_once("Don't know what interrupt to post for console.\n");
  66     //panic("Need implementation\n");
  67 }
  68
  69 void
  70 T1000::clearConsoleInt()
  71 {
  72     warn_once("Don't know what interrupt to clear for console.\n");
  73     //panic("Need implementation\n");
  74 }
  75
  76 void
  77 T1000::postPciInt(int line)
  78 {
  79     panic("Need implementation\n");
  80 }
  81
  82 void
  83 T1000::clearPciInt(int line)
  84 {
  85     panic("Need implementation\n");
  86 }
  87
  88 Addr
  89 T1000::pciToDma(Addr pciAddr) const
  90 {
  91     panic("Need implementation\n");
  92 }
  93
  94
  95 Addr
  96 T1000::calcConfigAddr(int bus, int dev, int func)
  97 {
  98     panic("Need implementation\n");
  99 }
 100
 101 void
 102 T1000::serialize(std::ostream &os)
 103 {
 104     panic("Need implementation\n");
 105 }
 106
 107 void
 108 T1000::unserialize(Checkpoint *cp, const std::string &section)
 109 {
 110     panic("Need implementation\n");
 111 }
 112
 113 BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
 114
 115     SimObjectParam<System *> system;
 116     SimObjectParam<IntrControl *> intrctrl;
 117
 118 END_DECLARE_SIM_OBJECT_PARAMS(T1000)
 119
 120 BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
 121
 122     INIT_PARAM(system, "system"),
 123     INIT_PARAM(intrctrl, "interrupt controller")
 124
 125 END_INIT_SIM_OBJECT_PARAMS(T1000)
 126
 127 CREATE_SIM_OBJECT(T1000)
 128 {
 129     return new T1000(getInstanceName(), system, intrctrl);
 130 }
 131
 132 REGISTER_SIM_OBJECT("T1000", T1000)