src/dev/storage/ide_ctrl.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Andrew Schultz
  29  *          Miguel Serrano
  30  */
  31
  32 /** @file
  33  * Simple PCI IDE controller with bus mastering capability and UDMA
  34  * modeled after controller in the Intel PIIX4 chip
  35  */
  36
  37 #ifndef __DEV_STORAGE_IDE_CTRL_HH__
  38 #define __DEV_STORAGE_IDE_CTRL_HH__
  39
  40 #include "base/bitunion.hh"
  41 #include "dev/io_device.hh"
  42 #include "dev/pci/device.hh"
  43 #include "params/IdeController.hh"
  44
  45 class IdeDisk;
  46
  47 /**
  48  * Device model for an Intel PIIX4 IDE controller
  49  */
  50
  51 class IdeController : public PciDevice
  52 {
  53   private:
  54     // Bus master IDE status register bit fields
  55     BitUnion8(BMIStatusReg)
  56         Bitfield<6> dmaCap0;
  57         Bitfield<5> dmaCap1;
  58         Bitfield<2> intStatus;
  59         Bitfield<1> dmaError;
  60         Bitfield<0> active;
  61     EndBitUnion(BMIStatusReg)
  62
  63     BitUnion8(BMICommandReg)
  64         Bitfield<3> rw;
  65         Bitfield<0> startStop;
  66     EndBitUnion(BMICommandReg)
  67
  68     struct Channel
  69     {
  70         std::string _name;
  71
  72         const std::string
  73         name()
  74         {
  75             return _name;
  76         }
  77
  78         /** Command and control block registers */
  79         Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
  80
  81         /** Registers used for bus master interface */
  82         struct BMIRegs
  83         {
  84             void reset() {
  85                 memset(static_cast<void *>(this), 0, sizeof(*this));
  86             }
  87
  88             BMICommandReg command;
  89             uint8_t reserved0;
  90             BMIStatusReg status;
  91             uint8_t reserved1;
  92             uint32_t bmidtp;
  93         } bmiRegs;
  94
  95         /** IDE disks connected to this controller */
  96         IdeDisk *master, *slave;
  97
  98         /** Currently selected disk */
  99         IdeDisk *selected;
 100
 101         bool selectBit;
 102
 103         void
 104         select(bool selSlave)
 105         {
 106             selectBit = selSlave;
 107             selected = selectBit ? slave : master;
 108         }
 109
 110         void accessCommand(Addr offset, int size, uint8_t *data, bool read);
 111         void accessControl(Addr offset, int size, uint8_t *data, bool read);
 112         void accessBMI(Addr offset, int size, uint8_t *data, bool read);
 113
 114         Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
 115         ~Channel();
 116
 117         void serialize(const std::string &base, std::ostream &os) const;
 118         void unserialize(const std::string &base, CheckpointIn &cp);
 119     };
 120
 121     Channel primary;
 122     Channel secondary;
 123
 124     /** Bus master interface (BMI) registers */
 125     Addr bmiAddr, bmiSize;
 126
 127     /** Registers used in device specific PCI configuration */
 128     uint16_t primaryTiming, secondaryTiming;
 129     uint8_t deviceTiming;
 130     uint8_t udmaControl;
 131     uint16_t udmaTiming;
 132     uint16_t ideConfig;
 133
 134     // Internal management variables
 135     bool ioEnabled;
 136     bool bmEnabled;
 137
 138     uint32_t ioShift, ctrlOffset;
 139
 140     void dispatchAccess(PacketPtr pkt, bool read);
 141
 142   public:
 143     typedef IdeControllerParams Params;
 144     const Params *params() const { return (const Params *)_params; }
 145     IdeController(Params *p);
 146
 147     /** See if a disk is selected based on its pointer */
 148     bool isDiskSelected(IdeDisk *diskPtr);
 149
 150     void intrPost();
 151
 152     Tick writeConfig(PacketPtr pkt) override;
 153     Tick readConfig(PacketPtr pkt) override;
 154
 155     void setDmaComplete(IdeDisk *disk);
 156
 157     Tick read(PacketPtr pkt) override;
 158     Tick write(PacketPtr pkt) override;
 159
 160     void serialize(CheckpointOut &cp) const override;
 161     void unserialize(CheckpointIn &cp) override;
 162 };
 163 #endif // __DEV_STORAGE_IDE_CTRL_HH_