src/dev/storage/ide_disk.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /** @file
  42  * Device model for an IDE disk
  43  */
  44
  45 #ifndef __DEV_STORAGE_IDE_DISK_HH__
  46 #define __DEV_STORAGE_IDE_DISK_HH__
  47
  48 #include "base/statistics.hh"
  49 #include "dev/io_device.hh"
  50 #include "dev/storage/disk_image.hh"
  51 #include "dev/storage/ide_atareg.h"
  52 #include "dev/storage/ide_ctrl.hh"
  53 #include "dev/storage/ide_wdcreg.h"
  54 #include "params/IdeDisk.hh"
  55 #include "sim/eventq.hh"
  56
  57 class ChunkGenerator;
  58
  59 #define DMA_BACKOFF_PERIOD      200
  60
  61 #define MAX_DMA_SIZE            0x20000  // 128K
  62 #define MAX_SINGLE_DMA_SIZE     0x10000
  63 #define MAX_MULTSECT            (128)
  64
  65 #define PRD_BASE_MASK  0xfffffffe
  66 #define PRD_COUNT_MASK 0xfffe
  67 #define PRD_EOT_MASK   0x8000
  68
  69 typedef struct PrdEntry {
  70     uint32_t baseAddr;
  71     uint16_t byteCount;
  72     uint16_t endOfTable;
  73 } PrdEntry_t;
  74
  75 class PrdTableEntry {
  76   public:
  77     PrdEntry_t entry;
  78
  79     uint32_t getBaseAddr()
  80     {
  81         return (entry.baseAddr & PRD_BASE_MASK);
  82     }
  83
  84     uint32_t getByteCount()
  85     {
  86         return ((entry.byteCount == 0) ? MAX_SINGLE_DMA_SIZE :
  87                 (entry.byteCount & PRD_COUNT_MASK));
  88     }
  89
  90     uint16_t getEOT()
  91     {
  92         return (entry.endOfTable & PRD_EOT_MASK);
  93     }
  94 };
  95
  96 #define DATA_OFFSET     (0)
  97 #define ERROR_OFFSET    (1)
  98 #define FEATURES_OFFSET (1)
  99 #define NSECTOR_OFFSET  (2)
 100 #define SECTOR_OFFSET   (3)
 101 #define LCYL_OFFSET     (4)
 102 #define HCYL_OFFSET     (5)
 103 #define SELECT_OFFSET   (6)
 104 #define DRIVE_OFFSET    (6)
 105 #define STATUS_OFFSET   (7)
 106 #define COMMAND_OFFSET  (7)
 107
 108 #define CONTROL_OFFSET  (2)
 109 #define ALTSTAT_OFFSET  (2)
 110
 111 #define SELECT_DEV_BIT  0x10
 112 #define CONTROL_RST_BIT 0x04
 113 #define CONTROL_IEN_BIT 0x02
 114 #define STATUS_BSY_BIT  0x80
 115 #define STATUS_DRDY_BIT 0x40
 116 #define STATUS_DRQ_BIT  0x08
 117 #define STATUS_SEEK_BIT 0x10
 118 #define STATUS_DF_BIT   0x20
 119 #define DRIVE_LBA_BIT   0x40
 120
 121 #define DEV0 (0)
 122 #define DEV1 (1)
 123
 124 typedef struct CommandReg {
 125     uint16_t data;
 126     uint8_t error;
 127     uint8_t sec_count;
 128     uint8_t sec_num;
 129     uint8_t cyl_low;
 130     uint8_t cyl_high;
 131     union {
 132         uint8_t drive;
 133         uint8_t head;
 134     };
 135     uint8_t command;
 136 } CommandReg_t;
 137
 138 typedef enum Events {
 139     None = 0,
 140     Transfer,
 141     ReadWait,
 142     WriteWait,
 143     PrdRead,
 144     DmaRead,
 145     DmaWrite
 146 } Events_t;
 147
 148 typedef enum DevAction {
 149     ACT_NONE = 0,
 150     ACT_CMD_WRITE,
 151     ACT_CMD_COMPLETE,
 152     ACT_CMD_ERROR,
 153     ACT_SELECT_WRITE,
 154     ACT_STAT_READ,
 155     ACT_DATA_READY,
 156     ACT_DATA_READ_BYTE,
 157     ACT_DATA_READ_SHORT,
 158     ACT_DATA_WRITE_BYTE,
 159     ACT_DATA_WRITE_SHORT,
 160     ACT_DMA_READY,
 161     ACT_DMA_DONE,
 162     ACT_SRST_SET,
 163     ACT_SRST_CLEAR
 164 } DevAction_t;
 165
 166 typedef enum DevState {
 167     // Device idle
 168     Device_Idle_S = 0,
 169     Device_Idle_SI,
 170     Device_Idle_NS,
 171
 172     // Software reset
 173     Device_Srst,
 174
 175     // Non-data commands
 176     Command_Execution,
 177
 178     // PIO data-in (data to host)
 179     Prepare_Data_In,
 180     Data_Ready_INTRQ_In,
 181     Transfer_Data_In,
 182
 183     // PIO data-out (data from host)
 184     Prepare_Data_Out,
 185     Data_Ready_INTRQ_Out,
 186     Transfer_Data_Out,
 187
 188     // DMA protocol
 189     Prepare_Data_Dma,
 190     Transfer_Data_Dma,
 191     Device_Dma_Abort
 192 } DevState_t;
 193
 194 typedef enum DmaState {
 195     Dma_Idle = 0,
 196     Dma_Start,
 197     Dma_Transfer
 198 } DmaState_t;
 199
 200 class IdeController;
 201
 202 /**
 203  * IDE Disk device model
 204  */
 205 class IdeDisk : public SimObject
 206 {
 207   protected:
 208     /** The IDE controller for this disk. */
 209     IdeController *ctrl;
 210     /** The image that contains the data of this disk. */
 211     DiskImage *image;
 212
 213   protected:
 214     /** The disk delay in microseconds. */
 215     int diskDelay;
 216
 217   private:
 218     /** Drive identification structure for this disk */
 219     struct ataparams driveID;
 220     /** Data buffer for transfers */
 221     uint8_t *dataBuffer;
 222     /** Number of bytes in command data transfer */
 223     uint32_t cmdBytes;
 224     /** Number of bytes left in command data transfer */
 225     uint32_t cmdBytesLeft;
 226     /** Number of bytes left in DRQ block */
 227     uint32_t drqBytesLeft;
 228     /** Current sector in access */
 229     uint32_t curSector;
 230     /** Command block registers */
 231     CommandReg_t cmdReg;
 232     /** Status register */
 233     uint8_t status;
 234     /** Interrupt enable bit */
 235     bool nIENBit;
 236     /** Device state */
 237     DevState_t devState;
 238     /** Dma state */
 239     DmaState_t dmaState;
 240     /** Dma transaction is a read */
 241     bool dmaRead;
 242     /** Size of OS pages. */
 243     Addr pageBytes;
 244     /** PRD table base address */
 245     uint32_t curPrdAddr;
 246     /** PRD entry */
 247     PrdTableEntry curPrd;
 248     /** Device ID (master=0/slave=1) */
 249     int devID;
 250     /** Interrupt pending */
 251     bool intrPending;
 252     /** DMA Aborted */
 253     bool dmaAborted;
 254
 255     Stats::Scalar dmaReadFullPages;
 256     Stats::Scalar dmaReadBytes;
 257     Stats::Scalar dmaReadTxs;
 258     Stats::Scalar dmaWriteFullPages;
 259     Stats::Scalar dmaWriteBytes;
 260     Stats::Scalar dmaWriteTxs;
 261
 262   public:
 263     typedef IdeDiskParams Params;
 264     IdeDisk(const Params *p);
 265
 266     /**
 267      * Delete the data buffer.
 268      */
 269     ~IdeDisk();
 270
 271     /**
 272      * Reset the device state
 273      */
 274     void reset(int id);
 275
 276     /**
 277      * Register Statistics
 278      */
 279     void regStats() override;
 280
 281     /**
 282      * Set the controller for this device
 283      * @param c The IDE controller
 284      */
 285     void
 286     setController(IdeController *c, Addr page_bytes)
 287     {
 288         panic_if(ctrl, "Cannot change the controller once set!\n");
 289         ctrl = c;
 290         pageBytes = page_bytes;
 291     }
 292
 293     // Device register read/write
 294     void readCommand(const Addr offset, int size, uint8_t *data);
 295     void readControl(const Addr offset, int size, uint8_t *data);
 296     void writeCommand(const Addr offset, int size, const uint8_t *data);
 297     void writeControl(const Addr offset, int size, const uint8_t *data);
 298
 299     // Start/abort functions
 300     void startDma(const uint32_t &prdTableBase);
 301     void abortDma();
 302
 303   private:
 304     void startCommand();
 305
 306     // Interrupt management
 307     void intrPost();
 308     void intrClear();
 309
 310     // DMA stuff
 311     void doDmaTransfer();
 312     EventFunctionWrapper dmaTransferEvent;
 313
 314     void doDmaDataRead();
 315
 316     void doDmaRead();
 317     ChunkGenerator *dmaReadCG;
 318     EventFunctionWrapper dmaReadWaitEvent;
 319
 320     void doDmaDataWrite();
 321
 322     void doDmaWrite();
 323     ChunkGenerator *dmaWriteCG;
 324     EventFunctionWrapper dmaWriteWaitEvent;
 325
 326     void dmaPrdReadDone();
 327     EventFunctionWrapper dmaPrdReadEvent;
 328
 329     void dmaReadDone();
 330     EventFunctionWrapper dmaReadEvent;
 331
 332     void dmaWriteDone();
 333     EventFunctionWrapper dmaWriteEvent;
 334
 335     // Disk image read/write
 336     void readDisk(uint32_t sector, uint8_t *data);
 337     void writeDisk(uint32_t sector, uint8_t *data);
 338
 339     // State machine management
 340     void updateState(DevAction_t action);
 341
 342     // Utility functions
 343     bool isBSYSet() { return (status & STATUS_BSY_BIT); }
 344     bool isIENSet() { return nIENBit; }
 345     bool isDEVSelect();
 346
 347     void setComplete()
 348     {
 349         // clear out the status byte
 350         status = 0;
 351         // set the DRDY bit
 352         status |= STATUS_DRDY_BIT;
 353         // set the SEEK bit
 354         status |= STATUS_SEEK_BIT;
 355     }
 356
 357     uint32_t getLBABase()
 358     {
 359         return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
 360                        (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
 361     }
 362
 363     inline Addr pciToDma(Addr pciAddr);
 364
 365     void serialize(CheckpointOut &cp) const override;
 366     void unserialize(CheckpointIn &cp) override;
 367 };
 368
 369
 370 #endif // __DEV_STORAGE_IDE_DISK_HH__