Only issue responses if we aren;t already blocked
[gem5.git] / src / dev / tsunami.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31 /** @file
32 * Implementation of Tsunami platform.
33 */
34
35 #include <deque>
36 #include <string>
37 #include <vector>
38
39 #include "cpu/intr_control.hh"
40 #include "dev/simconsole.hh"
41 #include "dev/tsunami_cchip.hh"
42 #include "dev/tsunami_pchip.hh"
43 #include "dev/tsunami_io.hh"
44 #include "dev/tsunami.hh"
45 #include "sim/builder.hh"
46 #include "sim/system.hh"
47
48 using namespace std;
49 //Should this be AlphaISA?
50 using namespace TheISA;
51
52 Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
53 : Platform(name, ic), system(s)
54 {
55 // set the back pointer from the system to myself
56 system->platform = this;
57
58 for (int i = 0; i < Tsunami::Max_CPUs; i++)
59 intr_sum_type[i] = 0;
60 }
61
62 Tick
63 Tsunami::intrFrequency()
64 {
65 return io->frequency();
66 }
67
68 void
69 Tsunami::postConsoleInt()
70 {
71 io->postPIC(0x10);
72 }
73
74 void
75 Tsunami::clearConsoleInt()
76 {
77 io->clearPIC(0x10);
78 }
79
80 void
81 Tsunami::postPciInt(int line)
82 {
83 cchip->postDRIR(line);
84 }
85
86 void
87 Tsunami::clearPciInt(int line)
88 {
89 cchip->clearDRIR(line);
90 }
91
92 Addr
93 Tsunami::pciToDma(Addr pciAddr) const
94 {
95 return pchip->translatePciToDma(pciAddr);
96 }
97
98
99 Addr
100 Tsunami::calcConfigAddr(int bus, int dev, int func)
101 {
102 return pchip->calcConfigAddr(bus, dev, func);
103 }
104
105 void
106 Tsunami::serialize(std::ostream &os)
107 {
108 SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
109 }
110
111 void
112 Tsunami::unserialize(Checkpoint *cp, const std::string &section)
113 {
114 UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
115 }
116
117 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
118
119 SimObjectParam<System *> system;
120 SimObjectParam<IntrControl *> intrctrl;
121
122 END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
123
124 BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
125
126 INIT_PARAM(system, "system"),
127 INIT_PARAM(intrctrl, "interrupt controller")
128
129 END_INIT_SIM_OBJECT_PARAMS(Tsunami)
130
131 CREATE_SIM_OBJECT(Tsunami)
132 {
133 return new Tsunami(getInstanceName(), system, intrctrl);
134 }
135
136 REGISTER_SIM_OBJECT("Tsunami", Tsunami)