2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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33 * Emulation of the Tsunami CChip CSRs
40 #include "arch/alpha/ev5.hh"
41 #include "base/trace.hh"
42 #include "dev/tsunami_cchip.hh"
43 #include "dev/tsunamireg.h"
44 #include "dev/tsunami.hh"
45 #include "mem/port.hh"
46 #include "cpu/thread_context.hh"
47 #include "cpu/intr_control.hh"
48 #include "sim/builder.hh"
49 #include "sim/system.hh"
52 //Should this be AlphaISA?
53 using namespace TheISA
;
55 TsunamiCChip::TsunamiCChip(Params
*p
)
56 : BasicPioDevice(p
), tsunami(p
->tsunami
)
64 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
70 //Put back pointer in tsunami
71 tsunami
->cchip
= this;
75 TsunamiCChip::read(Packet
*pkt
)
77 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
79 assert(pkt
->result
== Packet::Unknown
);
80 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
82 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
83 Addr daddr
= (pkt
->getAddr() - pioAddr
);
86 switch (pkt
->getSize()) {
88 case sizeof(uint64_t):
89 if (daddr
& TSDEV_CC_BDIMS
)
91 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
95 if (daddr
& TSDEV_CC_BDIRS
)
97 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
106 panic("TSDEV_CC_MTR not implemeted\n");
109 pkt
->set((ipint
<< 8) & 0xF | (itint
<< 4) & 0xF |
110 (pkt
->req
->getCpuNum() & 0x3));
146 panic("TSDEV_CC_PRBEN not implemented\n");
152 panic("TSDEV_CC_IICx not implemented\n");
158 panic("TSDEV_CC_MPRx not implemented\n");
167 panic("default in cchip read reached, accessing 0x%x\n");
171 case sizeof(uint32_t):
172 case sizeof(uint16_t):
173 case sizeof(uint8_t):
175 panic("invalid access size(?) for tsunami register!\n");
177 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
178 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
180 pkt
->result
= Packet::Success
;
185 TsunamiCChip::write(Packet
*pkt
)
187 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
188 Addr daddr
= pkt
->getAddr() - pioAddr
;
189 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
192 assert(pkt
->getSize() == sizeof(uint64_t));
194 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
196 bool supportedWrite
= false;
199 if (daddr
& TSDEV_CC_BDIMS
)
201 int number
= (daddr
>> 4) & 0x3F;
207 olddim
= dim
[number
];
208 olddir
= dir
[number
];
209 dim
[number
] = pkt
->get
<uint64_t>();
210 dir
[number
] = dim
[number
] & drir
;
211 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
213 bitvector
= ULL(1) << x
;
214 // Figure out which bits have changed
215 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
217 // The bit is now set and it wasn't before (set)
218 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
220 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
221 DPRINTF(Tsunami
, "dim write resulting in posting dir"
222 " interrupt to cpu %d\n", number
);
224 else if ((olddir
& bitvector
) &&
225 !(dir
[number
] & bitvector
))
227 // The bit was set and now its now clear and
228 // we were interrupting on that bit before
229 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
230 DPRINTF(Tsunami
, "dim write resulting in clear"
231 " dir interrupt to cpu %d\n", number
);
241 panic("TSDEV_CC_CSR write\n");
243 panic("TSDEV_CC_MTR write not implemented\n");
246 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
247 //If it is bit 12-15, this is an IPI post
250 supportedWrite
= true;
253 //If it is bit 8-11, this is an IPI clear
255 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
258 supportedWrite
= true;
261 //If it is the 4-7th bit, clear the RTC interrupt
263 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
266 supportedWrite
= true;
270 if (pkt
->get
<uint64_t>() & 0x10000000)
271 supportedWrite
= true;
274 panic("TSDEV_CC_MISC write not implemented\n");
281 panic("TSDEV_CC_AARx write not implemeted\n");
287 if(regnum
== TSDEV_CC_DIM0
)
289 else if(regnum
== TSDEV_CC_DIM1
)
291 else if(regnum
== TSDEV_CC_DIM2
)
300 olddim
= dim
[number
];
301 olddir
= dir
[number
];
302 dim
[number
] = pkt
->get
<uint64_t>();
303 dir
[number
] = dim
[number
] & drir
;
304 for(int x
= 0; x
< 64; x
++)
306 bitvector
= ULL(1) << x
;
307 // Figure out which bits have changed
308 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
310 // The bit is now set and it wasn't before (set)
311 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
313 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
314 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
316 else if ((olddir
& bitvector
) &&
317 !(dir
[number
] & bitvector
))
319 // The bit was set and now its now clear and
320 // we were interrupting on that bit before
321 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
322 DPRINTF(Tsunami
, "dim write resulting in clear"
323 " dir interrupt to cpu %d\n",
336 panic("TSDEV_CC_DIR write not implemented\n");
338 panic("TSDEV_CC_DRIR write not implemented\n");
340 panic("TSDEV_CC_PRBEN write not implemented\n");
345 panic("TSDEV_CC_IICx write not implemented\n");
350 panic("TSDEV_CC_MPRx write not implemented\n");
352 clearIPI(pkt
->get
<uint64_t>());
355 clearITI(pkt
->get
<uint64_t>());
358 reqIPI(pkt
->get
<uint64_t>());
361 panic("default in cchip read reached, accessing 0x%x\n");
363 } // not BIG_TSUNAMI write
364 pkt
->result
= Packet::Success
;
369 TsunamiCChip::clearIPI(uint64_t ipintr
)
371 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
372 assert(numcpus
<= Tsunami::Max_CPUs
);
375 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
376 // Check each cpu bit
377 uint64_t cpumask
= ULL(1) << cpunum
;
378 if (ipintr
& cpumask
) {
379 // Check if there is a pending ipi
380 if (ipint
& cpumask
) {
382 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
383 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
386 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
391 panic("Big IPI Clear, but not processors indicated\n");
395 TsunamiCChip::clearITI(uint64_t itintr
)
397 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
398 assert(numcpus
<= Tsunami::Max_CPUs
);
401 for (int i
=0; i
< numcpus
; i
++) {
402 uint64_t cpumask
= ULL(1) << i
;
403 if (itintr
& cpumask
& itint
) {
404 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
406 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
411 panic("Big ITI Clear, but not processors indicated\n");
415 TsunamiCChip::reqIPI(uint64_t ipreq
)
417 int numcpus
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
418 assert(numcpus
<= Tsunami::Max_CPUs
);
421 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
422 // Check each cpu bit
423 uint64_t cpumask
= ULL(1) << cpunum
;
424 if (ipreq
& cpumask
) {
425 // Check if there is already an ipi (bits 8:11)
426 if (!(ipint
& cpumask
)) {
428 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
429 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
432 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
437 panic("Big IPI Request, but not processors indicated\n");
442 TsunamiCChip::postRTC()
444 int size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
445 assert(size
<= Tsunami::Max_CPUs
);
447 for (int i
= 0; i
< size
; i
++) {
448 uint64_t cpumask
= ULL(1) << i
;
449 if (!(cpumask
& itint
)) {
451 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
452 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d", i
);
459 TsunamiCChip::postDRIR(uint32_t interrupt
)
461 uint64_t bitvector
= ULL(1) << interrupt
;
462 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
463 assert(size
<= Tsunami::Max_CPUs
);
466 for(int i
=0; i
< size
; i
++) {
467 dir
[i
] = dim
[i
] & drir
;
468 if (dim
[i
] & bitvector
) {
469 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
470 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
471 "interrupt %d\n",i
, interrupt
);
477 TsunamiCChip::clearDRIR(uint32_t interrupt
)
479 uint64_t bitvector
= ULL(1) << interrupt
;
480 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->threadContexts
.size();
481 assert(size
<= Tsunami::Max_CPUs
);
483 if (drir
& bitvector
)
486 for(int i
=0; i
< size
; i
++) {
487 if (dir
[i
] & bitvector
) {
488 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
489 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
490 "interrupt %d\n",i
, interrupt
);
493 dir
[i
] = dim
[i
] & drir
;
497 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
502 TsunamiCChip::serialize(std::ostream
&os
)
504 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
505 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
506 SERIALIZE_SCALAR(ipint
);
507 SERIALIZE_SCALAR(itint
);
508 SERIALIZE_SCALAR(drir
);
512 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
514 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
515 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
516 UNSERIALIZE_SCALAR(ipint
);
517 UNSERIALIZE_SCALAR(itint
);
518 UNSERIALIZE_SCALAR(drir
);
521 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
523 Param
<Addr
> pio_addr
;
524 Param
<Tick
> pio_latency
;
525 SimObjectParam
<Platform
*> platform
;
526 SimObjectParam
<System
*> system
;
527 SimObjectParam
<Tsunami
*> tsunami
;
529 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
531 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
533 INIT_PARAM(pio_addr
, "Device Address"),
534 INIT_PARAM(pio_latency
, "Programmed IO latency"),
535 INIT_PARAM(platform
, "platform"),
536 INIT_PARAM(system
, "system object"),
537 INIT_PARAM(tsunami
, "Tsunami")
539 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
541 CREATE_SIM_OBJECT(TsunamiCChip
)
543 TsunamiCChip::Params
*p
= new TsunamiCChip::Params
;
544 p
->name
= getInstanceName();
545 p
->pio_addr
= pio_addr
;
546 p
->pio_delay
= pio_latency
;
547 p
->platform
= platform
;
549 p
->tsunami
= tsunami
;
550 return new TsunamiCChip(p
);
553 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip
)