src/dev/tsunami_cchip.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Emulation of the Tsunami CChip CSRs
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "arch/alpha/ev5.hh"
  38 #include "base/trace.hh"
  39 #include "dev/tsunami_cchip.hh"
  40 #include "dev/tsunamireg.h"
  41 #include "dev/tsunami.hh"
  42 #include "mem/port.hh"
  43 #include "cpu/exec_context.hh"
  44 #include "cpu/intr_control.hh"
  45 #include "sim/builder.hh"
  46 #include "sim/system.hh"
  47
  48 using namespace std;
  49 //Should this be AlphaISA?
  50 using namespace TheISA;
  51
  52 TsunamiCChip::TsunamiCChip(Params *p)
  53     : BasicPioDevice(p), tsunami(p->tsunami)
  54 {
  55     pioSize = 0xfffffff;
  56
  57     drir = 0;
  58     ipint = 0;
  59     itint = 0;
  60
  61     for (int x = 0; x < Tsunami::Max_CPUs; x++)
  62     {
  63         dim[x] = 0;
  64         dir[x] = 0;
  65     }
  66
  67     //Put back pointer in tsunami
  68     tsunami->cchip = this;
  69 }
  70
  71 Tick
  72 TsunamiCChip::read(Packet *pkt)
  73 {
  74     DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
  75
  76     assert(pkt->result == Packet::Unknown);
  77     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  78
  79     Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
  80     Addr daddr = (pkt->getAddr() - pioAddr);
  81
  82     pkt->allocate();
  83     switch (pkt->getSize()) {
  84
  85       case sizeof(uint64_t):
  86           if (daddr & TSDEV_CC_BDIMS)
  87           {
  88               pkt->set(dim[(daddr >> 4) & 0x3F]);
  89               break;
  90           }
  91
  92           if (daddr & TSDEV_CC_BDIRS)
  93           {
  94               pkt->set(dir[(daddr >> 4) & 0x3F]);
  95               break;
  96           }
  97
  98           switch(regnum) {
  99               case TSDEV_CC_CSR:
 100                   pkt->set(0x0);
 101                   break;
 102               case TSDEV_CC_MTR:
 103                   panic("TSDEV_CC_MTR not implemeted\n");
 104                    break;
 105               case TSDEV_CC_MISC:
 106                   pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
 107                                      (pkt->req->getCpuNum() & 0x3));
 108                   break;
 109               case TSDEV_CC_AAR0:
 110               case TSDEV_CC_AAR1:
 111               case TSDEV_CC_AAR2:
 112               case TSDEV_CC_AAR3:
 113                   pkt->set(0);
 114                   break;
 115               case TSDEV_CC_DIM0:
 116                   pkt->set(dim[0]);
 117                   break;
 118               case TSDEV_CC_DIM1:
 119                   pkt->set(dim[1]);
 120                   break;
 121               case TSDEV_CC_DIM2:
 122                   pkt->set(dim[2]);
 123                   break;
 124               case TSDEV_CC_DIM3:
 125                   pkt->set(dim[3]);
 126                   break;
 127               case TSDEV_CC_DIR0:
 128                   pkt->set(dir[0]);
 129                   break;
 130               case TSDEV_CC_DIR1:
 131                   pkt->set(dir[1]);
 132                   break;
 133               case TSDEV_CC_DIR2:
 134                   pkt->set(dir[2]);
 135                   break;
 136               case TSDEV_CC_DIR3:
 137                   pkt->set(dir[3]);
 138                   break;
 139               case TSDEV_CC_DRIR:
 140                   pkt->set(drir);
 141                   break;
 142               case TSDEV_CC_PRBEN:
 143                   panic("TSDEV_CC_PRBEN not implemented\n");
 144                   break;
 145               case TSDEV_CC_IIC0:
 146               case TSDEV_CC_IIC1:
 147               case TSDEV_CC_IIC2:
 148               case TSDEV_CC_IIC3:
 149                   panic("TSDEV_CC_IICx not implemented\n");
 150                   break;
 151               case TSDEV_CC_MPR0:
 152               case TSDEV_CC_MPR1:
 153               case TSDEV_CC_MPR2:
 154               case TSDEV_CC_MPR3:
 155                   panic("TSDEV_CC_MPRx not implemented\n");
 156                   break;
 157               case TSDEV_CC_IPIR:
 158                   pkt->set(ipint);
 159                   break;
 160               case TSDEV_CC_ITIR:
 161                   pkt->set(itint);
 162                   break;
 163               default:
 164                   panic("default in cchip read reached, accessing 0x%x\n");
 165            } // uint64_t
 166
 167       break;
 168       case sizeof(uint32_t):
 169       case sizeof(uint16_t):
 170       case sizeof(uint8_t):
 171       default:
 172         panic("invalid access size(?) for tsunami register!\n");
 173     }
 174     DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
 175             regnum, pkt->getSize(), pkt->get<uint64_t>());
 176
 177     pkt->result = Packet::Success;
 178     return pioDelay;
 179 }
 180
 181 Tick
 182 TsunamiCChip::write(Packet *pkt)
 183 {
 184     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 185     Addr daddr = pkt->getAddr() - pioAddr;
 186     Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
 187
 188
 189     assert(pkt->getSize() == sizeof(uint64_t));
 190
 191     DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
 192
 193     bool supportedWrite = false;
 194
 195
 196     if (daddr & TSDEV_CC_BDIMS)
 197     {
 198         int number = (daddr >> 4) & 0x3F;
 199
 200         uint64_t bitvector;
 201         uint64_t olddim;
 202         uint64_t olddir;
 203
 204         olddim = dim[number];
 205         olddir = dir[number];
 206         dim[number] = pkt->get<uint64_t>();
 207         dir[number] = dim[number] & drir;
 208         for(int x = 0; x < Tsunami::Max_CPUs; x++)
 209         {
 210             bitvector = ULL(1) << x;
 211             // Figure out which bits have changed
 212             if ((dim[number] & bitvector) != (olddim & bitvector))
 213             {
 214                 // The bit is now set and it wasn't before (set)
 215                 if((dim[number] & bitvector) && (dir[number] & bitvector))
 216                 {
 217                     tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 218                     DPRINTF(Tsunami, "dim write resulting in posting dir"
 219                             " interrupt to cpu %d\n", number);
 220                 }
 221                 else if ((olddir & bitvector) &&
 222                         !(dir[number] & bitvector))
 223                 {
 224                     // The bit was set and now its now clear and
 225                     // we were interrupting on that bit before
 226                     tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 227                     DPRINTF(Tsunami, "dim write resulting in clear"
 228                             " dir interrupt to cpu %d\n", number);
 229
 230                 }
 231
 232
 233             }
 234         }
 235     } else {
 236         switch(regnum) {
 237           case TSDEV_CC_CSR:
 238               panic("TSDEV_CC_CSR write\n");
 239           case TSDEV_CC_MTR:
 240               panic("TSDEV_CC_MTR write not implemented\n");
 241           case TSDEV_CC_MISC:
 242             uint64_t ipreq;
 243             ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
 244             //If it is bit 12-15, this is an IPI post
 245             if (ipreq) {
 246                 reqIPI(ipreq);
 247                 supportedWrite = true;
 248             }
 249
 250             //If it is bit 8-11, this is an IPI clear
 251             uint64_t ipintr;
 252             ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
 253             if (ipintr) {
 254                 clearIPI(ipintr);
 255                 supportedWrite = true;
 256             }
 257
 258             //If it is the 4-7th bit, clear the RTC interrupt
 259             uint64_t itintr;
 260               itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
 261             if (itintr) {
 262                   clearITI(itintr);
 263                 supportedWrite = true;
 264             }
 265
 266               // ignore NXMs
 267               if (pkt->get<uint64_t>() & 0x10000000)
 268                   supportedWrite = true;
 269
 270             if(!supportedWrite)
 271                   panic("TSDEV_CC_MISC write not implemented\n");
 272
 273             break;
 274             case TSDEV_CC_AAR0:
 275             case TSDEV_CC_AAR1:
 276             case TSDEV_CC_AAR2:
 277             case TSDEV_CC_AAR3:
 278                 panic("TSDEV_CC_AARx write not implemeted\n");
 279             case TSDEV_CC_DIM0:
 280             case TSDEV_CC_DIM1:
 281             case TSDEV_CC_DIM2:
 282             case TSDEV_CC_DIM3:
 283                 int number;
 284                 if(regnum == TSDEV_CC_DIM0)
 285                     number = 0;
 286                 else if(regnum == TSDEV_CC_DIM1)
 287                     number = 1;
 288                 else if(regnum == TSDEV_CC_DIM2)
 289                     number = 2;
 290                 else
 291                     number = 3;
 292
 293                 uint64_t bitvector;
 294                 uint64_t olddim;
 295                 uint64_t olddir;
 296
 297                 olddim = dim[number];
 298                 olddir = dir[number];
 299                 dim[number] = pkt->get<uint64_t>();
 300                 dir[number] = dim[number] & drir;
 301                 for(int x = 0; x < 64; x++)
 302                 {
 303                     bitvector = ULL(1) << x;
 304                     // Figure out which bits have changed
 305                     if ((dim[number] & bitvector) != (olddim & bitvector))
 306                     {
 307                         // The bit is now set and it wasn't before (set)
 308                         if((dim[number] & bitvector) && (dir[number] & bitvector))
 309                         {
 310                           tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 311                           DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
 312                         }
 313                         else if ((olddir & bitvector) &&
 314                                 !(dir[number] & bitvector))
 315                         {
 316                             // The bit was set and now its now clear and
 317                             // we were interrupting on that bit before
 318                             tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 319                           DPRINTF(Tsunami, "dim write resulting in clear"
 320                                     " dir interrupt to cpu %d\n",
 321                                     x);
 322
 323                         }
 324
 325
 326                     }
 327                 }
 328                 break;
 329             case TSDEV_CC_DIR0:
 330             case TSDEV_CC_DIR1:
 331             case TSDEV_CC_DIR2:
 332             case TSDEV_CC_DIR3:
 333                 panic("TSDEV_CC_DIR write not implemented\n");
 334             case TSDEV_CC_DRIR:
 335                 panic("TSDEV_CC_DRIR write not implemented\n");
 336             case TSDEV_CC_PRBEN:
 337                 panic("TSDEV_CC_PRBEN write not implemented\n");
 338             case TSDEV_CC_IIC0:
 339             case TSDEV_CC_IIC1:
 340             case TSDEV_CC_IIC2:
 341             case TSDEV_CC_IIC3:
 342                 panic("TSDEV_CC_IICx write not implemented\n");
 343             case TSDEV_CC_MPR0:
 344             case TSDEV_CC_MPR1:
 345             case TSDEV_CC_MPR2:
 346             case TSDEV_CC_MPR3:
 347                 panic("TSDEV_CC_MPRx write not implemented\n");
 348             case TSDEV_CC_IPIR:
 349                 clearIPI(pkt->get<uint64_t>());
 350                 break;
 351             case TSDEV_CC_ITIR:
 352                 clearITI(pkt->get<uint64_t>());
 353                 break;
 354             case TSDEV_CC_IPIQ:
 355                 reqIPI(pkt->get<uint64_t>());
 356                 break;
 357             default:
 358               panic("default in cchip read reached, accessing 0x%x\n");
 359         }  // swtich(regnum)
 360     } // not BIG_TSUNAMI write
 361     pkt->result = Packet::Success;
 362     return pioDelay;
 363 }
 364
 365 void
 366 TsunamiCChip::clearIPI(uint64_t ipintr)
 367 {
 368     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 369     assert(numcpus <= Tsunami::Max_CPUs);
 370
 371     if (ipintr) {
 372         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 373             // Check each cpu bit
 374             uint64_t cpumask = ULL(1) << cpunum;
 375             if (ipintr & cpumask) {
 376                 // Check if there is a pending ipi
 377                 if (ipint & cpumask) {
 378                     ipint &= ~cpumask;
 379                     tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 380                     DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
 381                 }
 382                 else
 383                     warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
 384             }
 385         }
 386     }
 387     else
 388         panic("Big IPI Clear, but not processors indicated\n");
 389 }
 390
 391 void
 392 TsunamiCChip::clearITI(uint64_t itintr)
 393 {
 394     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 395     assert(numcpus <= Tsunami::Max_CPUs);
 396
 397     if (itintr) {
 398         for (int i=0; i < numcpus; i++) {
 399             uint64_t cpumask = ULL(1) << i;
 400             if (itintr & cpumask & itint) {
 401                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
 402                 itint &= ~cpumask;
 403                 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
 404             }
 405         }
 406     }
 407     else
 408         panic("Big ITI Clear, but not processors indicated\n");
 409 }
 410
 411 void
 412 TsunamiCChip::reqIPI(uint64_t ipreq)
 413 {
 414     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 415     assert(numcpus <= Tsunami::Max_CPUs);
 416
 417     if (ipreq) {
 418         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 419             // Check each cpu bit
 420             uint64_t cpumask = ULL(1) << cpunum;
 421             if (ipreq & cpumask) {
 422                 // Check if there is already an ipi (bits 8:11)
 423                 if (!(ipint & cpumask)) {
 424                     ipint  |= cpumask;
 425                     tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 426                     DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
 427                 }
 428                 else
 429                     warn("post IPI for CPU=%d, but IPI already\n", cpunum);
 430             }
 431         }
 432     }
 433     else
 434         panic("Big IPI Request, but not processors indicated\n");
 435 }
 436
 437
 438 void
 439 TsunamiCChip::postRTC()
 440 {
 441     int size = tsunami->intrctrl->cpu->system->execContexts.size();
 442     assert(size <= Tsunami::Max_CPUs);
 443
 444     for (int i = 0; i < size; i++) {
 445         uint64_t cpumask = ULL(1) << i;
 446        if (!(cpumask & itint)) {
 447            itint |= cpumask;
 448            tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
 449            DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
 450        }
 451     }
 452
 453 }
 454
 455 void
 456 TsunamiCChip::postDRIR(uint32_t interrupt)
 457 {
 458     uint64_t bitvector = ULL(1) << interrupt;
 459     uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
 460     assert(size <= Tsunami::Max_CPUs);
 461     drir |= bitvector;
 462
 463     for(int i=0; i < size; i++) {
 464         dir[i] = dim[i] & drir;
 465        if (dim[i] & bitvector) {
 466               tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
 467               DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
 468                         "interrupt %d\n",i, interrupt);
 469        }
 470     }
 471 }
 472
 473 void
 474 TsunamiCChip::clearDRIR(uint32_t interrupt)
 475 {
 476     uint64_t bitvector = ULL(1) << interrupt;
 477     uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
 478     assert(size <= Tsunami::Max_CPUs);
 479
 480     if (drir & bitvector)
 481     {
 482         drir &= ~bitvector;
 483         for(int i=0; i < size; i++) {
 484            if (dir[i] & bitvector) {
 485                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
 486                DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
 487                     "interrupt %d\n",i, interrupt);
 488
 489            }
 490            dir[i] = dim[i] & drir;
 491         }
 492     }
 493     else
 494         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 495 }
 496
 497
 498 void
 499 TsunamiCChip::serialize(std::ostream &os)
 500 {
 501     SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 502     SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 503     SERIALIZE_SCALAR(ipint);
 504     SERIALIZE_SCALAR(itint);
 505     SERIALIZE_SCALAR(drir);
 506 }
 507
 508 void
 509 TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
 510 {
 511     UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 512     UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 513     UNSERIALIZE_SCALAR(ipint);
 514     UNSERIALIZE_SCALAR(itint);
 515     UNSERIALIZE_SCALAR(drir);
 516 }
 517
 518 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 519
 520     Param<Addr> pio_addr;
 521     Param<Tick> pio_latency;
 522     SimObjectParam<Platform *> platform;
 523     SimObjectParam<System *> system;
 524     SimObjectParam<Tsunami *> tsunami;
 525
 526 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 527
 528 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 529
 530     INIT_PARAM(pio_addr, "Device Address"),
 531     INIT_PARAM(pio_latency, "Programmed IO latency"),
 532     INIT_PARAM(platform, "platform"),
 533     INIT_PARAM(system, "system object"),
 534     INIT_PARAM(tsunami, "Tsunami")
 535
 536 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 537
 538 CREATE_SIM_OBJECT(TsunamiCChip)
 539 {
 540     TsunamiCChip::Params *p = new TsunamiCChip::Params;
 541     p->name = getInstanceName();
 542     p->pio_addr = pio_addr;
 543     p->pio_delay = pio_latency;
 544     p->platform = platform;
 545     p->system = system;
 546     p->tsunami = tsunami;
 547     return new TsunamiCChip(p);
 548 }
 549
 550 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)