2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Emulation of the Tsunami CChip CSRs
37 #include "arch/alpha/ev5.hh"
38 #include "base/trace.hh"
39 #include "dev/tsunami_cchip.hh"
40 #include "dev/tsunamireg.h"
41 #include "dev/tsunami.hh"
42 #include "mem/port.hh"
43 #include "cpu/exec_context.hh"
44 #include "cpu/intr_control.hh"
45 #include "sim/builder.hh"
46 #include "sim/system.hh"
49 //Should this be AlphaISA?
50 using namespace TheISA
;
52 TsunamiCChip::TsunamiCChip(Params
*p
)
53 : BasicPioDevice(p
), tsunami(p
->tsunami
)
61 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
67 //Put back pointer in tsunami
68 tsunami
->cchip
= this;
72 TsunamiCChip::read(Packet
*pkt
)
74 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
76 assert(pkt
->result
== Packet::Unknown
);
77 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
79 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
80 Addr daddr
= (pkt
->getAddr() - pioAddr
);
83 switch (pkt
->getSize()) {
85 case sizeof(uint64_t):
86 if (daddr
& TSDEV_CC_BDIMS
)
88 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
92 if (daddr
& TSDEV_CC_BDIRS
)
94 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
103 panic("TSDEV_CC_MTR not implemeted\n");
106 pkt
->set((ipint
<< 8) & 0xF | (itint
<< 4) & 0xF |
107 (pkt
->req
->getCpuNum() & 0x3));
143 panic("TSDEV_CC_PRBEN not implemented\n");
149 panic("TSDEV_CC_IICx not implemented\n");
155 panic("TSDEV_CC_MPRx not implemented\n");
164 panic("default in cchip read reached, accessing 0x%x\n");
168 case sizeof(uint32_t):
169 case sizeof(uint16_t):
170 case sizeof(uint8_t):
172 panic("invalid access size(?) for tsunami register!\n");
174 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
175 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
177 pkt
->result
= Packet::Success
;
182 TsunamiCChip::write(Packet
*pkt
)
184 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
185 Addr daddr
= pkt
->getAddr() - pioAddr
;
186 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
189 assert(pkt
->getSize() == sizeof(uint64_t));
191 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
193 bool supportedWrite
= false;
196 if (daddr
& TSDEV_CC_BDIMS
)
198 int number
= (daddr
>> 4) & 0x3F;
204 olddim
= dim
[number
];
205 olddir
= dir
[number
];
206 dim
[number
] = pkt
->get
<uint64_t>();
207 dir
[number
] = dim
[number
] & drir
;
208 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
210 bitvector
= ULL(1) << x
;
211 // Figure out which bits have changed
212 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
214 // The bit is now set and it wasn't before (set)
215 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
217 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
218 DPRINTF(Tsunami
, "dim write resulting in posting dir"
219 " interrupt to cpu %d\n", number
);
221 else if ((olddir
& bitvector
) &&
222 !(dir
[number
] & bitvector
))
224 // The bit was set and now its now clear and
225 // we were interrupting on that bit before
226 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
227 DPRINTF(Tsunami
, "dim write resulting in clear"
228 " dir interrupt to cpu %d\n", number
);
238 panic("TSDEV_CC_CSR write\n");
240 panic("TSDEV_CC_MTR write not implemented\n");
243 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
244 //If it is bit 12-15, this is an IPI post
247 supportedWrite
= true;
250 //If it is bit 8-11, this is an IPI clear
252 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
255 supportedWrite
= true;
258 //If it is the 4-7th bit, clear the RTC interrupt
260 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
263 supportedWrite
= true;
267 if (pkt
->get
<uint64_t>() & 0x10000000)
268 supportedWrite
= true;
271 panic("TSDEV_CC_MISC write not implemented\n");
278 panic("TSDEV_CC_AARx write not implemeted\n");
284 if(regnum
== TSDEV_CC_DIM0
)
286 else if(regnum
== TSDEV_CC_DIM1
)
288 else if(regnum
== TSDEV_CC_DIM2
)
297 olddim
= dim
[number
];
298 olddir
= dir
[number
];
299 dim
[number
] = pkt
->get
<uint64_t>();
300 dir
[number
] = dim
[number
] & drir
;
301 for(int x
= 0; x
< 64; x
++)
303 bitvector
= ULL(1) << x
;
304 // Figure out which bits have changed
305 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
307 // The bit is now set and it wasn't before (set)
308 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
310 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
311 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
313 else if ((olddir
& bitvector
) &&
314 !(dir
[number
] & bitvector
))
316 // The bit was set and now its now clear and
317 // we were interrupting on that bit before
318 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
319 DPRINTF(Tsunami
, "dim write resulting in clear"
320 " dir interrupt to cpu %d\n",
333 panic("TSDEV_CC_DIR write not implemented\n");
335 panic("TSDEV_CC_DRIR write not implemented\n");
337 panic("TSDEV_CC_PRBEN write not implemented\n");
342 panic("TSDEV_CC_IICx write not implemented\n");
347 panic("TSDEV_CC_MPRx write not implemented\n");
349 clearIPI(pkt
->get
<uint64_t>());
352 clearITI(pkt
->get
<uint64_t>());
355 reqIPI(pkt
->get
<uint64_t>());
358 panic("default in cchip read reached, accessing 0x%x\n");
360 } // not BIG_TSUNAMI write
361 pkt
->result
= Packet::Success
;
366 TsunamiCChip::clearIPI(uint64_t ipintr
)
368 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
369 assert(numcpus
<= Tsunami::Max_CPUs
);
372 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
373 // Check each cpu bit
374 uint64_t cpumask
= ULL(1) << cpunum
;
375 if (ipintr
& cpumask
) {
376 // Check if there is a pending ipi
377 if (ipint
& cpumask
) {
379 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
380 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
383 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
388 panic("Big IPI Clear, but not processors indicated\n");
392 TsunamiCChip::clearITI(uint64_t itintr
)
394 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
395 assert(numcpus
<= Tsunami::Max_CPUs
);
398 for (int i
=0; i
< numcpus
; i
++) {
399 uint64_t cpumask
= ULL(1) << i
;
400 if (itintr
& cpumask
& itint
) {
401 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
403 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
408 panic("Big ITI Clear, but not processors indicated\n");
412 TsunamiCChip::reqIPI(uint64_t ipreq
)
414 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
415 assert(numcpus
<= Tsunami::Max_CPUs
);
418 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
419 // Check each cpu bit
420 uint64_t cpumask
= ULL(1) << cpunum
;
421 if (ipreq
& cpumask
) {
422 // Check if there is already an ipi (bits 8:11)
423 if (!(ipint
& cpumask
)) {
425 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
426 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
429 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
434 panic("Big IPI Request, but not processors indicated\n");
439 TsunamiCChip::postRTC()
441 int size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
442 assert(size
<= Tsunami::Max_CPUs
);
444 for (int i
= 0; i
< size
; i
++) {
445 uint64_t cpumask
= ULL(1) << i
;
446 if (!(cpumask
& itint
)) {
448 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
449 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d", i
);
456 TsunamiCChip::postDRIR(uint32_t interrupt
)
458 uint64_t bitvector
= ULL(1) << interrupt
;
459 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
460 assert(size
<= Tsunami::Max_CPUs
);
463 for(int i
=0; i
< size
; i
++) {
464 dir
[i
] = dim
[i
] & drir
;
465 if (dim
[i
] & bitvector
) {
466 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
467 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
468 "interrupt %d\n",i
, interrupt
);
474 TsunamiCChip::clearDRIR(uint32_t interrupt
)
476 uint64_t bitvector
= ULL(1) << interrupt
;
477 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
478 assert(size
<= Tsunami::Max_CPUs
);
480 if (drir
& bitvector
)
483 for(int i
=0; i
< size
; i
++) {
484 if (dir
[i
] & bitvector
) {
485 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
486 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
487 "interrupt %d\n",i
, interrupt
);
490 dir
[i
] = dim
[i
] & drir
;
494 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
499 TsunamiCChip::serialize(std::ostream
&os
)
501 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
502 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
503 SERIALIZE_SCALAR(ipint
);
504 SERIALIZE_SCALAR(itint
);
505 SERIALIZE_SCALAR(drir
);
509 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
511 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
512 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
513 UNSERIALIZE_SCALAR(ipint
);
514 UNSERIALIZE_SCALAR(itint
);
515 UNSERIALIZE_SCALAR(drir
);
518 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
520 Param
<Addr
> pio_addr
;
521 Param
<Tick
> pio_latency
;
522 SimObjectParam
<Platform
*> platform
;
523 SimObjectParam
<System
*> system
;
524 SimObjectParam
<Tsunami
*> tsunami
;
526 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
528 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
530 INIT_PARAM(pio_addr
, "Device Address"),
531 INIT_PARAM(pio_latency
, "Programmed IO latency"),
532 INIT_PARAM(platform
, "platform"),
533 INIT_PARAM(system
, "system object"),
534 INIT_PARAM(tsunami
, "Tsunami")
536 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
538 CREATE_SIM_OBJECT(TsunamiCChip
)
540 TsunamiCChip::Params
*p
= new TsunamiCChip::Params
;
541 p
->name
= getInstanceName();
542 p
->pio_addr
= pio_addr
;
543 p
->pio_delay
= pio_latency
;
544 p
->platform
= platform
;
546 p
->tsunami
= tsunami
;
547 return new TsunamiCChip(p
);
550 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip
)