2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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30 * Emulation of the Tsunami CChip CSRs
37 #include "arch/alpha/ev5.hh"
38 #include "base/trace.hh"
39 #include "dev/tsunami_cchip.hh"
40 #include "dev/tsunamireg.h"
41 #include "dev/tsunami.hh"
42 #include "mem/port.hh"
43 #include "cpu/exec_context.hh"
44 #include "cpu/intr_control.hh"
45 #include "sim/builder.hh"
46 #include "sim/system.hh"
49 //Should this be AlphaISA?
50 using namespace TheISA
;
52 TsunamiCChip::TsunamiCChip(Params
*p
)
53 : BasicPioDevice(p
), tsunami(p
->tsunami
)
61 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
67 //Put back pointer in tsunami
68 tsunami
->cchip
= this;
72 TsunamiCChip::read(Packet
*pkt
)
74 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
76 assert(pkt
->result
== Packet::Unknown
);
77 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
79 pkt
->time
+= pioDelay
;
80 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6;
81 Addr daddr
= (pkt
->getAddr() - pioAddr
);
84 switch (pkt
->getSize()) {
86 case sizeof(uint64_t):
87 if (daddr
& TSDEV_CC_BDIMS
)
89 pkt
->set(dim
[(daddr
>> 4) & 0x3F]);
93 if (daddr
& TSDEV_CC_BDIRS
)
95 pkt
->set(dir
[(daddr
>> 4) & 0x3F]);
104 panic("TSDEV_CC_MTR not implemeted\n");
107 pkt
->set((ipint
<< 8) & 0xF | (itint
<< 4) & 0xF |
108 (pkt
->req
->getCpuNum() & 0x3));
144 panic("TSDEV_CC_PRBEN not implemented\n");
150 panic("TSDEV_CC_IICx not implemented\n");
156 panic("TSDEV_CC_MPRx not implemented\n");
165 panic("default in cchip read reached, accessing 0x%x\n");
169 case sizeof(uint32_t):
170 case sizeof(uint16_t):
171 case sizeof(uint8_t):
173 panic("invalid access size(?) for tsunami register!\n");
175 DPRINTF(Tsunami
, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
176 regnum
, pkt
->getSize(), pkt
->get
<uint64_t>());
178 pkt
->result
= Packet::Success
;
183 TsunamiCChip::write(Packet
*pkt
)
185 pkt
->time
+= pioDelay
;
188 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
189 Addr daddr
= pkt
->getAddr() - pioAddr
;
190 Addr regnum
= (pkt
->getAddr() - pioAddr
) >> 6 ;
193 assert(pkt
->getSize() == sizeof(uint64_t));
195 DPRINTF(Tsunami
, "write - addr=%#x value=%#x\n", pkt
->getAddr(), pkt
->get
<uint64_t>());
197 bool supportedWrite
= false;
200 if (daddr
& TSDEV_CC_BDIMS
)
202 int number
= (daddr
>> 4) & 0x3F;
208 olddim
= dim
[number
];
209 olddir
= dir
[number
];
210 dim
[number
] = pkt
->get
<uint64_t>();
211 dir
[number
] = dim
[number
] & drir
;
212 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
214 bitvector
= ULL(1) << x
;
215 // Figure out which bits have changed
216 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
218 // The bit is now set and it wasn't before (set)
219 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
221 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
222 DPRINTF(Tsunami
, "dim write resulting in posting dir"
223 " interrupt to cpu %d\n", number
);
225 else if ((olddir
& bitvector
) &&
226 !(dir
[number
] & bitvector
))
228 // The bit was set and now its now clear and
229 // we were interrupting on that bit before
230 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
231 DPRINTF(Tsunami
, "dim write resulting in clear"
232 " dir interrupt to cpu %d\n", number
);
242 panic("TSDEV_CC_CSR write\n");
244 panic("TSDEV_CC_MTR write not implemented\n");
247 ipreq
= (pkt
->get
<uint64_t>() >> 12) & 0xF;
248 //If it is bit 12-15, this is an IPI post
251 supportedWrite
= true;
254 //If it is bit 8-11, this is an IPI clear
256 ipintr
= (pkt
->get
<uint64_t>() >> 8) & 0xF;
259 supportedWrite
= true;
262 //If it is the 4-7th bit, clear the RTC interrupt
264 itintr
= (pkt
->get
<uint64_t>() >> 4) & 0xF;
267 supportedWrite
= true;
271 if (pkt
->get
<uint64_t>() & 0x10000000)
272 supportedWrite
= true;
275 panic("TSDEV_CC_MISC write not implemented\n");
282 panic("TSDEV_CC_AARx write not implemeted\n");
288 if(regnum
== TSDEV_CC_DIM0
)
290 else if(regnum
== TSDEV_CC_DIM1
)
292 else if(regnum
== TSDEV_CC_DIM2
)
301 olddim
= dim
[number
];
302 olddir
= dir
[number
];
303 dim
[number
] = pkt
->get
<uint64_t>();
304 dir
[number
] = dim
[number
] & drir
;
305 for(int x
= 0; x
< 64; x
++)
307 bitvector
= ULL(1) << x
;
308 // Figure out which bits have changed
309 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
311 // The bit is now set and it wasn't before (set)
312 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
314 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
315 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
317 else if ((olddir
& bitvector
) &&
318 !(dir
[number
] & bitvector
))
320 // The bit was set and now its now clear and
321 // we were interrupting on that bit before
322 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
323 DPRINTF(Tsunami
, "dim write resulting in clear"
324 " dir interrupt to cpu %d\n",
337 panic("TSDEV_CC_DIR write not implemented\n");
339 panic("TSDEV_CC_DRIR write not implemented\n");
341 panic("TSDEV_CC_PRBEN write not implemented\n");
346 panic("TSDEV_CC_IICx write not implemented\n");
351 panic("TSDEV_CC_MPRx write not implemented\n");
353 clearIPI(pkt
->get
<uint64_t>());
356 clearITI(pkt
->get
<uint64_t>());
359 reqIPI(pkt
->get
<uint64_t>());
362 panic("default in cchip read reached, accessing 0x%x\n");
364 } // not BIG_TSUNAMI write
365 pkt
->result
= Packet::Success
;
370 TsunamiCChip::clearIPI(uint64_t ipintr
)
372 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
373 assert(numcpus
<= Tsunami::Max_CPUs
);
376 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
377 // Check each cpu bit
378 uint64_t cpumask
= ULL(1) << cpunum
;
379 if (ipintr
& cpumask
) {
380 // Check if there is a pending ipi
381 if (ipint
& cpumask
) {
383 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
384 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
387 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
392 panic("Big IPI Clear, but not processors indicated\n");
396 TsunamiCChip::clearITI(uint64_t itintr
)
398 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
399 assert(numcpus
<= Tsunami::Max_CPUs
);
402 for (int i
=0; i
< numcpus
; i
++) {
403 uint64_t cpumask
= ULL(1) << i
;
404 if (itintr
& cpumask
& itint
) {
405 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
407 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
412 panic("Big ITI Clear, but not processors indicated\n");
416 TsunamiCChip::reqIPI(uint64_t ipreq
)
418 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
419 assert(numcpus
<= Tsunami::Max_CPUs
);
422 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
423 // Check each cpu bit
424 uint64_t cpumask
= ULL(1) << cpunum
;
425 if (ipreq
& cpumask
) {
426 // Check if there is already an ipi (bits 8:11)
427 if (!(ipint
& cpumask
)) {
429 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
430 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
433 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
438 panic("Big IPI Request, but not processors indicated\n");
443 TsunamiCChip::postRTC()
445 int size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
446 assert(size
<= Tsunami::Max_CPUs
);
448 for (int i
= 0; i
< size
; i
++) {
449 uint64_t cpumask
= ULL(1) << i
;
450 if (!(cpumask
& itint
)) {
452 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
453 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d", i
);
460 TsunamiCChip::postDRIR(uint32_t interrupt
)
462 uint64_t bitvector
= ULL(1) << interrupt
;
463 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
464 assert(size
<= Tsunami::Max_CPUs
);
467 for(int i
=0; i
< size
; i
++) {
468 dir
[i
] = dim
[i
] & drir
;
469 if (dim
[i
] & bitvector
) {
470 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
471 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
472 "interrupt %d\n",i
, interrupt
);
478 TsunamiCChip::clearDRIR(uint32_t interrupt
)
480 uint64_t bitvector
= ULL(1) << interrupt
;
481 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
482 assert(size
<= Tsunami::Max_CPUs
);
484 if (drir
& bitvector
)
487 for(int i
=0; i
< size
; i
++) {
488 if (dir
[i
] & bitvector
) {
489 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
490 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
491 "interrupt %d\n",i
, interrupt
);
494 dir
[i
] = dim
[i
] & drir
;
498 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
503 TsunamiCChip::serialize(std::ostream
&os
)
505 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
506 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
507 SERIALIZE_SCALAR(ipint
);
508 SERIALIZE_SCALAR(itint
);
509 SERIALIZE_SCALAR(drir
);
513 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
515 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
516 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
517 UNSERIALIZE_SCALAR(ipint
);
518 UNSERIALIZE_SCALAR(itint
);
519 UNSERIALIZE_SCALAR(drir
);
522 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
524 Param
<Addr
> pio_addr
;
525 Param
<Tick
> pio_latency
;
526 SimObjectParam
<Platform
*> platform
;
527 SimObjectParam
<System
*> system
;
528 SimObjectParam
<Tsunami
*> tsunami
;
530 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
532 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
534 INIT_PARAM(pio_addr
, "Device Address"),
535 INIT_PARAM(pio_latency
, "Programmed IO latency"),
536 INIT_PARAM(platform
, "platform"),
537 INIT_PARAM(system
, "system object"),
538 INIT_PARAM(tsunami
, "Tsunami")
540 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
542 CREATE_SIM_OBJECT(TsunamiCChip
)
544 TsunamiCChip::Params
*p
= new TsunamiCChip::Params
;
545 p
->name
= getInstanceName();
546 p
->pio_addr
= pio_addr
;
547 p
->pio_delay
= pio_latency
;
548 p
->platform
= platform
;
550 p
->tsunami
= tsunami
;
551 return new TsunamiCChip(p
);
554 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip
)