src/dev/tsunami_io.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  *          Andrew Schultz
  30  *          Miguel Serrano
  31  */
  32
  33 /** @file
  34  * Tsunami I/O including PIC, PIT, RTC, DMA
  35  */
  36
  37 #include <sys/time.h>
  38
  39 #include <deque>
  40 #include <string>
  41 #include <vector>
  42
  43 #include "base/trace.hh"
  44 #include "dev/pitreg.h"
  45 #include "dev/rtcreg.h"
  46 #include "dev/tsunami_cchip.hh"
  47 #include "dev/tsunami.hh"
  48 #include "dev/tsunami_io.hh"
  49 #include "dev/tsunamireg.h"
  50 #include "mem/port.hh"
  51 #include "sim/builder.hh"
  52 #include "sim/system.hh"
  53
  54 using namespace std;
  55 //Should this be AlphaISA?
  56 using namespace TheISA;
  57
  58 TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i)
  59     : _name(name), event(t, i), addr(0)
  60 {
  61     memset(clock_data, 0, sizeof(clock_data));
  62     stat_regA = RTCA_32768HZ | RTCA_1024HZ;
  63     stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
  64 }
  65
  66 void
  67 TsunamiIO::RTC::set_time(time_t t)
  68 {
  69     struct tm tm;
  70     gmtime_r(&t, &tm);
  71
  72     sec = tm.tm_sec;
  73     min = tm.tm_min;
  74     hour = tm.tm_hour;
  75     wday = tm.tm_wday + 1;
  76     mday = tm.tm_mday;
  77     mon = tm.tm_mon + 1;
  78     year = tm.tm_year;
  79
  80     DPRINTFN("Real-time clock set to %s", asctime(&tm));
  81 }
  82
  83 void
  84 TsunamiIO::RTC::writeAddr(const uint8_t data)
  85 {
  86     if (data <= RTC_STAT_REGD)
  87         addr = data;
  88     else
  89         panic("RTC addresses over 0xD are not implemented.\n");
  90 }
  91
  92 void
  93 TsunamiIO::RTC::writeData(const uint8_t data)
  94 {
  95     if (addr < RTC_STAT_REGA)
  96         clock_data[addr] = data;
  97     else {
  98         switch (addr) {
  99           case RTC_STAT_REGA:
 100             if (data != (RTCA_32768HZ | RTCA_1024HZ))
 101                 panic("Unimplemented RTC register A value write!\n");
 102             stat_regA = data;
 103             break;
 104           case RTC_STAT_REGB:
 105             if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
 106                 panic("Write to RTC reg B bits that are not implemented!\n");
 107
 108             if (data & RTCB_PRDC_IE) {
 109                 if (!event.scheduled())
 110                     event.scheduleIntr();
 111             } else {
 112                 if (event.scheduled())
 113                     event.deschedule();
 114             }
 115             stat_regB = data;
 116             break;
 117           case RTC_STAT_REGC:
 118           case RTC_STAT_REGD:
 119             panic("RTC status registers C and D are not implemented.\n");
 120             break;
 121         }
 122     }
 123 }
 124
 125 uint8_t
 126 TsunamiIO::RTC::readData()
 127 {
 128     if (addr < RTC_STAT_REGA)
 129         return clock_data[addr];
 130     else {
 131         switch (addr) {
 132           case RTC_STAT_REGA:
 133             // toggle UIP bit for linux
 134             stat_regA ^= RTCA_UIP;
 135             return stat_regA;
 136             break;
 137           case RTC_STAT_REGB:
 138             return stat_regB;
 139             break;
 140           case RTC_STAT_REGC:
 141           case RTC_STAT_REGD:
 142             return 0x00;
 143             break;
 144           default:
 145             panic("Shouldn't be here");
 146         }
 147     }
 148 }
 149
 150 void
 151 TsunamiIO::RTC::serialize(const string &base, ostream &os)
 152 {
 153     paramOut(os, base + ".addr", addr);
 154     arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
 155     paramOut(os, base + ".stat_regA", stat_regA);
 156     paramOut(os, base + ".stat_regB", stat_regB);
 157 }
 158
 159 void
 160 TsunamiIO::RTC::unserialize(const string &base, Checkpoint *cp,
 161                             const string &section)
 162 {
 163     paramIn(cp, section, base + ".addr", addr);
 164     arrayParamIn(cp, section, base + ".clock_data", clock_data,
 165                  sizeof(clock_data));
 166     paramIn(cp, section, base + ".stat_regA", stat_regA);
 167     paramIn(cp, section, base + ".stat_regB", stat_regB);
 168
 169     // We're not unserializing the event here, but we need to
 170     // rescehedule the event since curTick was moved forward by the
 171     // checkpoint
 172     event.reschedule(curTick + event.interval);
 173 }
 174
 175 TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i)
 176     : Event(&mainEventQueue), tsunami(t), interval(i)
 177 {
 178     DPRINTF(MC146818, "RTC Event Initilizing\n");
 179     schedule(curTick + interval);
 180 }
 181
 182 void
 183 TsunamiIO::RTC::RTCEvent::scheduleIntr()
 184 {
 185   schedule(curTick + interval);
 186 }
 187
 188 void
 189 TsunamiIO::RTC::RTCEvent::process()
 190 {
 191     DPRINTF(MC146818, "RTC Timer Interrupt\n");
 192     schedule(curTick + interval);
 193     //Actually interrupt the processor here
 194     tsunami->cchip->postRTC();
 195 }
 196
 197 const char *
 198 TsunamiIO::RTC::RTCEvent::description()
 199 {
 200     return "tsunami RTC interrupt";
 201 }
 202
 203 TsunamiIO::PITimer::PITimer(const string &name)
 204     : _name(name), counter0(name + ".counter0"), counter1(name + ".counter1"),
 205       counter2(name + ".counter2")
 206 {
 207     counter[0] = &counter0;
 208     counter[1] = &counter0;
 209     counter[2] = &counter0;
 210 }
 211
 212 void
 213 TsunamiIO::PITimer::writeControl(const uint8_t data)
 214 {
 215     int rw;
 216     int sel;
 217
 218     sel = GET_CTRL_SEL(data);
 219
 220     if (sel == PIT_READ_BACK)
 221        panic("PITimer Read-Back Command is not implemented.\n");
 222
 223     rw = GET_CTRL_RW(data);
 224
 225     if (rw == PIT_RW_LATCH_COMMAND)
 226         counter[sel]->latchCount();
 227     else {
 228         counter[sel]->setRW(rw);
 229         counter[sel]->setMode(GET_CTRL_MODE(data));
 230         counter[sel]->setBCD(GET_CTRL_BCD(data));
 231     }
 232 }
 233
 234 void
 235 TsunamiIO::PITimer::serialize(const string &base, ostream &os)
 236 {
 237     // serialize the counters
 238     counter0.serialize(base + ".counter0", os);
 239     counter1.serialize(base + ".counter1", os);
 240     counter2.serialize(base + ".counter2", os);
 241 }
 242
 243 void
 244 TsunamiIO::PITimer::unserialize(const string &base, Checkpoint *cp,
 245                                 const string &section)
 246 {
 247     // unserialze the counters
 248     counter0.unserialize(base + ".counter0", cp, section);
 249     counter1.unserialize(base + ".counter1", cp, section);
 250     counter2.unserialize(base + ".counter2", cp, section);
 251 }
 252
 253 TsunamiIO::PITimer::Counter::Counter(const string &name)
 254     : _name(name), event(this), count(0), latched_count(0), period(0),
 255       mode(0), output_high(false), latch_on(false), read_byte(LSB),
 256       write_byte(LSB)
 257 {
 258
 259 }
 260
 261 void
 262 TsunamiIO::PITimer::Counter::latchCount()
 263 {
 264     // behave like a real latch
 265     if(!latch_on) {
 266         latch_on = true;
 267         read_byte = LSB;
 268         latched_count = count;
 269     }
 270 }
 271
 272 uint8_t
 273 TsunamiIO::PITimer::Counter::read()
 274 {
 275     if (latch_on) {
 276         switch (read_byte) {
 277           case LSB:
 278             read_byte = MSB;
 279             return (uint8_t)latched_count;
 280             break;
 281           case MSB:
 282             read_byte = LSB;
 283             latch_on = false;
 284             return latched_count >> 8;
 285             break;
 286           default:
 287             panic("Shouldn't be here");
 288         }
 289     } else {
 290         switch (read_byte) {
 291           case LSB:
 292             read_byte = MSB;
 293             return (uint8_t)count;
 294             break;
 295           case MSB:
 296             read_byte = LSB;
 297             return count >> 8;
 298             break;
 299           default:
 300             panic("Shouldn't be here");
 301         }
 302     }
 303 }
 304
 305 void
 306 TsunamiIO::PITimer::Counter::write(const uint8_t data)
 307 {
 308     switch (write_byte) {
 309       case LSB:
 310         count = (count & 0xFF00) | data;
 311
 312         if (event.scheduled())
 313           event.deschedule();
 314         output_high = false;
 315         write_byte = MSB;
 316         break;
 317
 318       case MSB:
 319         count = (count & 0x00FF) | (data << 8);
 320         period = count;
 321
 322         if (period > 0) {
 323             DPRINTF(Tsunami, "Timer set to curTick + %d\n",
 324                     count * event.interval);
 325             event.schedule(curTick + count * event.interval);
 326         }
 327         write_byte = LSB;
 328         break;
 329     }
 330 }
 331
 332 void
 333 TsunamiIO::PITimer::Counter::setRW(int rw_val)
 334 {
 335     if (rw_val != PIT_RW_16BIT)
 336         panic("Only LSB/MSB read/write is implemented.\n");
 337 }
 338
 339 void
 340 TsunamiIO::PITimer::Counter::setMode(int mode_val)
 341 {
 342     if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN &&
 343        mode_val != PIT_MODE_SQWAVE)
 344         panic("PIT mode %#x is not implemented: \n", mode_val);
 345
 346     mode = mode_val;
 347 }
 348
 349 void
 350 TsunamiIO::PITimer::Counter::setBCD(int bcd_val)
 351 {
 352     if (bcd_val != PIT_BCD_FALSE)
 353         panic("PITimer does not implement BCD counts.\n");
 354 }
 355
 356 bool
 357 TsunamiIO::PITimer::Counter::outputHigh()
 358 {
 359     return output_high;
 360 }
 361
 362 void
 363 TsunamiIO::PITimer::Counter::serialize(const string &base, ostream &os)
 364 {
 365     paramOut(os, base + ".count", count);
 366     paramOut(os, base + ".latched_count", latched_count);
 367     paramOut(os, base + ".period", period);
 368     paramOut(os, base + ".mode", mode);
 369     paramOut(os, base + ".output_high", output_high);
 370     paramOut(os, base + ".latch_on", latch_on);
 371     paramOut(os, base + ".read_byte", read_byte);
 372     paramOut(os, base + ".write_byte", write_byte);
 373
 374     Tick event_tick = 0;
 375     if (event.scheduled())
 376         event_tick = event.when();
 377     paramOut(os, base + ".event_tick", event_tick);
 378 }
 379
 380 void
 381 TsunamiIO::PITimer::Counter::unserialize(const string &base, Checkpoint *cp,
 382                                          const string &section)
 383 {
 384     paramIn(cp, section, base + ".count", count);
 385     paramIn(cp, section, base + ".latched_count", latched_count);
 386     paramIn(cp, section, base + ".period", period);
 387     paramIn(cp, section, base + ".mode", mode);
 388     paramIn(cp, section, base + ".output_high", output_high);
 389     paramIn(cp, section, base + ".latch_on", latch_on);
 390     paramIn(cp, section, base + ".read_byte", read_byte);
 391     paramIn(cp, section, base + ".write_byte", write_byte);
 392
 393     Tick event_tick;
 394     paramIn(cp, section, base + ".event_tick", event_tick);
 395     if (event_tick)
 396         event.schedule(event_tick);
 397 }
 398
 399 TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
 400     : Event(&mainEventQueue)
 401 {
 402     interval = (Tick)(Clock::Float::s / 1193180.0);
 403     counter = c_ptr;
 404 }
 405
 406 void
 407 TsunamiIO::PITimer::Counter::CounterEvent::process()
 408 {
 409     DPRINTF(Tsunami, "Timer Interrupt\n");
 410     switch (counter->mode) {
 411       case PIT_MODE_INTTC:
 412         counter->output_high = true;
 413       case PIT_MODE_RATEGEN:
 414       case PIT_MODE_SQWAVE:
 415         break;
 416       default:
 417         panic("Unimplemented PITimer mode.\n");
 418     }
 419 }
 420
 421 const char *
 422 TsunamiIO::PITimer::Counter::CounterEvent::description()
 423 {
 424     return "tsunami 8254 Interval timer";
 425 }
 426
 427 TsunamiIO::TsunamiIO(Params *p)
 428     : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
 429       rtc(p->name + ".rtc", p->tsunami, p->frequency)
 430 {
 431     pioSize = 0xff;
 432
 433     // set the back pointer from tsunami to myself
 434     tsunami->io = this;
 435
 436     timerData = 0;
 437     rtc.set_time(p->init_time == 0 ? time(NULL) : p->init_time);
 438     picr = 0;
 439     picInterrupting = false;
 440 }
 441
 442 Tick
 443 TsunamiIO::frequency() const
 444 {
 445     return Clock::Frequency / params()->frequency;
 446 }
 447
 448 Tick
 449 TsunamiIO::read(Packet *pkt)
 450 {
 451     assert(pkt->result == Packet::Unknown);
 452     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 453
 454     Addr daddr = pkt->getAddr() - pioAddr;
 455
 456     DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
 457             pkt->getSize(), daddr);
 458
 459     pkt->allocate();
 460
 461     if (pkt->getSize() == sizeof(uint8_t)) {
 462         switch(daddr) {
 463           // PIC1 mask read
 464           case TSDEV_PIC1_MASK:
 465             pkt->set(~mask1);
 466             break;
 467           case TSDEV_PIC2_MASK:
 468             pkt->set(~mask2);
 469             break;
 470           case TSDEV_PIC1_ISR:
 471               // !!! If this is modified 64bit case needs to be too
 472               // Pal code has to do a 64 bit physical read because there is
 473               // no load physical byte instruction
 474               pkt->set(picr);
 475               break;
 476           case TSDEV_PIC2_ISR:
 477               // PIC2 not implemnted... just return 0
 478               pkt->set(0x00);
 479               break;
 480           case TSDEV_TMR0_DATA:
 481             pkt->set(pitimer.counter0.read());
 482             break;
 483           case TSDEV_TMR1_DATA:
 484             pkt->set(pitimer.counter1.read());
 485             break;
 486           case TSDEV_TMR2_DATA:
 487             pkt->set(pitimer.counter2.read());
 488             break;
 489           case TSDEV_RTC_DATA:
 490             pkt->set(rtc.readData());
 491             break;
 492           case TSDEV_CTRL_PORTB:
 493             if (pitimer.counter2.outputHigh())
 494                 pkt->set(PORTB_SPKR_HIGH);
 495             else
 496                 pkt->set(0x00);
 497             break;
 498           default:
 499             panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
 500         }
 501     } else if (pkt->getSize() == sizeof(uint64_t)) {
 502         if (daddr == TSDEV_PIC1_ISR)
 503             pkt->set<uint64_t>(picr);
 504         else
 505            panic("I/O Read - invalid addr - va %#x size %d\n",
 506                    pkt->getAddr(), pkt->getSize());
 507     } else {
 508        panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
 509     }
 510     pkt->result = Packet::Success;
 511     return pioDelay;
 512 }
 513
 514 Tick
 515 TsunamiIO::write(Packet *pkt)
 516 {
 517     assert(pkt->result == Packet::Unknown);
 518     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 519     Addr daddr = pkt->getAddr() - pioAddr;
 520
 521     DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
 522             pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
 523
 524     assert(pkt->getSize() == sizeof(uint8_t));
 525
 526     switch(daddr) {
 527       case TSDEV_PIC1_MASK:
 528         mask1 = ~(pkt->get<uint8_t>());
 529         if ((picr & mask1) && !picInterrupting) {
 530             picInterrupting = true;
 531             tsunami->cchip->postDRIR(55);
 532             DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
 533         }
 534         if ((!(picr & mask1)) && picInterrupting) {
 535             picInterrupting = false;
 536             tsunami->cchip->clearDRIR(55);
 537             DPRINTF(Tsunami, "clearing pic interrupt\n");
 538         }
 539         break;
 540       case TSDEV_PIC2_MASK:
 541         mask2 = pkt->get<uint8_t>();
 542         //PIC2 Not implemented to interrupt
 543         break;
 544       case TSDEV_PIC1_ACK:
 545         // clear the interrupt on the PIC
 546         picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
 547         if (!(picr & mask1))
 548             tsunami->cchip->clearDRIR(55);
 549         break;
 550       case TSDEV_DMA1_MODE:
 551         mode1 = pkt->get<uint8_t>();
 552         break;
 553       case TSDEV_DMA2_MODE:
 554         mode2 = pkt->get<uint8_t>();
 555         break;
 556       case TSDEV_TMR0_DATA:
 557         pitimer.counter0.write(pkt->get<uint8_t>());
 558         break;
 559       case TSDEV_TMR1_DATA:
 560         pitimer.counter1.write(pkt->get<uint8_t>());
 561         break;
 562       case TSDEV_TMR2_DATA:
 563         pitimer.counter2.write(pkt->get<uint8_t>());
 564         break;
 565       case TSDEV_TMR_CTRL:
 566         pitimer.writeControl(pkt->get<uint8_t>());
 567         break;
 568       case TSDEV_RTC_ADDR:
 569         rtc.writeAddr(pkt->get<uint8_t>());
 570         break;
 571       case TSDEV_RTC_DATA:
 572         rtc.writeData(pkt->get<uint8_t>());
 573         break;
 574       case TSDEV_KBD:
 575       case TSDEV_DMA1_CMND:
 576       case TSDEV_DMA2_CMND:
 577       case TSDEV_DMA1_MMASK:
 578       case TSDEV_DMA2_MMASK:
 579       case TSDEV_PIC2_ACK:
 580       case TSDEV_DMA1_RESET:
 581       case TSDEV_DMA2_RESET:
 582       case TSDEV_DMA1_MASK:
 583       case TSDEV_DMA2_MASK:
 584       case TSDEV_CTRL_PORTB:
 585         break;
 586       default:
 587         panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
 588     }
 589
 590     pkt->result = Packet::Success;
 591     return pioDelay;
 592 }
 593
 594 void
 595 TsunamiIO::postPIC(uint8_t bitvector)
 596 {
 597     //PIC2 Is not implemented, because nothing of interest there
 598     picr |= bitvector;
 599     if (picr & mask1) {
 600         tsunami->cchip->postDRIR(55);
 601         DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
 602     }
 603 }
 604
 605 void
 606 TsunamiIO::clearPIC(uint8_t bitvector)
 607 {
 608     //PIC2 Is not implemented, because nothing of interest there
 609     picr &= ~bitvector;
 610     if (!(picr & mask1)) {
 611         tsunami->cchip->clearDRIR(55);
 612         DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
 613     }
 614 }
 615
 616 void
 617 TsunamiIO::serialize(ostream &os)
 618 {
 619     SERIALIZE_SCALAR(timerData);
 620     SERIALIZE_SCALAR(mask1);
 621     SERIALIZE_SCALAR(mask2);
 622     SERIALIZE_SCALAR(mode1);
 623     SERIALIZE_SCALAR(mode2);
 624     SERIALIZE_SCALAR(picr);
 625     SERIALIZE_SCALAR(picInterrupting);
 626
 627     // Serialize the timers
 628     pitimer.serialize("pitimer", os);
 629     rtc.serialize("rtc", os);
 630 }
 631
 632 void
 633 TsunamiIO::unserialize(Checkpoint *cp, const string &section)
 634 {
 635     UNSERIALIZE_SCALAR(timerData);
 636     UNSERIALIZE_SCALAR(mask1);
 637     UNSERIALIZE_SCALAR(mask2);
 638     UNSERIALIZE_SCALAR(mode1);
 639     UNSERIALIZE_SCALAR(mode2);
 640     UNSERIALIZE_SCALAR(picr);
 641     UNSERIALIZE_SCALAR(picInterrupting);
 642
 643     // Unserialize the timers
 644     pitimer.unserialize("pitimer", cp, section);
 645     rtc.unserialize("rtc", cp, section);
 646 }
 647
 648 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
 649
 650     Param<Addr> pio_addr;
 651     Param<Tick> pio_latency;
 652     Param<Tick> frequency;
 653     SimObjectParam<Platform *> platform;
 654     SimObjectParam<System *> system;
 655     Param<time_t> time;
 656     SimObjectParam<Tsunami *> tsunami;
 657
 658 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
 659
 660 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
 661
 662     INIT_PARAM(pio_addr, "Device Address"),
 663     INIT_PARAM(pio_latency, "Programmed IO latency"),
 664     INIT_PARAM(frequency, "clock interrupt frequency"),
 665     INIT_PARAM(platform, "platform"),
 666     INIT_PARAM(system, "system object"),
 667     INIT_PARAM(time, "System time to use (0 for actual time"),
 668     INIT_PARAM(tsunami, "Tsunami")
 669
 670 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
 671
 672 CREATE_SIM_OBJECT(TsunamiIO)
 673 {
 674     TsunamiIO::Params *p = new TsunamiIO::Params;
 675     p->frequency = frequency;
 676     p->name = getInstanceName();
 677     p->pio_addr = pio_addr;
 678     p->pio_delay = pio_latency;
 679     p->platform = platform;
 680     p->system = system;
 681     p->init_time = time;
 682     p->tsunami = tsunami;
 683     return new TsunamiIO(p);
 684 }
 685
 686 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)