2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "base/trace.hh"
41 #include "dev/tsunami_pchip.hh"
42 #include "dev/tsunamireg.h"
43 #include "dev/tsunami.hh"
44 #include "mem/packet.hh"
45 #include "sim/builder.hh"
46 #include "sim/system.hh"
49 //Should this be AlphaISA?
50 using namespace TheISA
;
52 TsunamiPChip::TsunamiPChip(Params
*p
)
57 for (int i
= 0; i
< 4; i
++) {
63 // initialize pchip control register
64 pctl
= (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
66 //Set back pointer in tsunami
67 p
->tsunami
->pchip
= this;
71 TsunamiPChip::read(Packet
*pkt
)
73 assert(pkt
->result
== Packet::Unknown
);
74 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
77 Addr daddr
= (pkt
->getAddr() - pioAddr
) >> 6;;
78 assert(pkt
->getSize() == sizeof(uint64_t));
81 DPRINTF(Tsunami
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
124 panic("PC_PLAT not implemented\n");
126 panic("PC_RES not implemented\n");
127 case TSDEV_PC_PERROR
:
128 pkt
->set((uint64_t)0x00);
130 case TSDEV_PC_PERRMASK
:
131 pkt
->set((uint64_t)0x00);
133 case TSDEV_PC_PERRSET
:
134 panic("PC_PERRSET not implemented\n");
136 panic("PC_TLBIV not implemented\n");
138 pkt
->set((uint64_t)0x00); // shouldn't be readable, but linux
140 case TSDEV_PC_PMONCTL
:
141 panic("PC_PMONCTL not implemented\n");
142 case TSDEV_PC_PMONCNT
:
143 panic("PC_PMONCTN not implemented\n");
145 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
147 pkt
->result
= Packet::Success
;
153 TsunamiPChip::write(Packet
*pkt
)
155 assert(pkt
->result
== Packet::Unknown
);
156 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
157 Addr daddr
= (pkt
->getAddr() - pioAddr
) >> 6;
159 assert(pkt
->getSize() == sizeof(uint64_t));
161 DPRINTF(Tsunami
, "write - va=%#x size=%d \n", pkt
->getAddr(), pkt
->getSize());
165 wsba
[0] = pkt
->get
<uint64_t>();
168 wsba
[1] = pkt
->get
<uint64_t>();
171 wsba
[2] = pkt
->get
<uint64_t>();
174 wsba
[3] = pkt
->get
<uint64_t>();
177 wsm
[0] = pkt
->get
<uint64_t>();
180 wsm
[1] = pkt
->get
<uint64_t>();
183 wsm
[2] = pkt
->get
<uint64_t>();
186 wsm
[3] = pkt
->get
<uint64_t>();
189 tba
[0] = pkt
->get
<uint64_t>();
192 tba
[1] = pkt
->get
<uint64_t>();
195 tba
[2] = pkt
->get
<uint64_t>();
198 tba
[3] = pkt
->get
<uint64_t>();
201 pctl
= pkt
->get
<uint64_t>();
204 panic("PC_PLAT not implemented\n");
206 panic("PC_RES not implemented\n");
207 case TSDEV_PC_PERROR
:
209 case TSDEV_PC_PERRMASK
:
210 panic("PC_PERRMASK not implemented\n");
211 case TSDEV_PC_PERRSET
:
212 panic("PC_PERRSET not implemented\n");
214 panic("PC_TLBIV not implemented\n");
216 break; // value ignored, supposted to invalidate SG TLB
217 case TSDEV_PC_PMONCTL
:
218 panic("PC_PMONCTL not implemented\n");
219 case TSDEV_PC_PMONCNT
:
220 panic("PC_PMONCTN not implemented\n");
222 panic("Default in PChip write reached reading 0x%x\n", daddr
);
226 pkt
->result
= Packet::Success
;
230 #define DMA_ADDR_MASK ULL(0x3ffffffff)
233 TsunamiPChip::translatePciToDma(Addr busAddr
)
235 // compare the address to the window base registers
236 uint64_t tbaMask
= 0;
239 uint64_t windowMask
= 0;
240 uint64_t windowBase
= 0;
242 uint64_t pteEntry
= 0;
248 DPRINTF(IdeDisk
, "Translation for bus address: %#x\n", busAddr
);
249 for (int i
= 0; i
< 4; i
++) {
250 DPRINTF(IdeDisk
, "(%d) base:%#x mask:%#x\n",
253 windowBase
= wsba
[i
];
254 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
256 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
257 DPRINTF(IdeDisk
, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
258 i
, windowBase
, windowMask
, (busAddr
& windowMask
),
259 (windowBase
& windowMask
));
264 for (int i
= 0; i
< 4; i
++) {
266 windowBase
= wsba
[i
];
267 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
269 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
271 if (wsba
[i
] & 0x1) { // see if enabled
272 if (wsba
[i
] & 0x2) { // see if SG bit is set
274 This currently is faked by just doing a direct
275 read from memory, however, to be realistic, this
276 needs to actually do a bus transaction. The process
277 is explained in the tsunami documentation on page
278 10-12 and basically munges the address to look up a
279 PTE from a table in memory and then uses that mapping
280 to create an address for the SG page
283 tbaMask
= ~(((wsm
[i
] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
284 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
285 pteAddr
= (tba
[i
] & tbaMask
) | ((busAddr
& baMask
) >> 10);
287 pioPort
->readBlob(pteAddr
, (uint8_t*)&pteEntry
, sizeof(uint64_t));
289 dmaAddr
= ((pteEntry
& ~ULL(0x1)) << 12) | (busAddr
& ULL(0x1fff));
292 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | ULL(0xfffff);
294 dmaAddr
= (tba
[i
] & tbaMask
) | (busAddr
& baMask
);
297 return (dmaAddr
& DMA_ADDR_MASK
);
302 // if no match was found, then return the original address
306 TsunamiPChip::calcConfigAddr(int bus
, int dev
, int func
)
312 return TsunamiPciBus0Config
| (func
<< 8) | (dev
<< 11);
318 TsunamiPChip::serialize(std::ostream
&os
)
320 SERIALIZE_SCALAR(pctl
);
321 SERIALIZE_ARRAY(wsba
, 4);
322 SERIALIZE_ARRAY(wsm
, 4);
323 SERIALIZE_ARRAY(tba
, 4);
327 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
329 UNSERIALIZE_SCALAR(pctl
);
330 UNSERIALIZE_ARRAY(wsba
, 4);
331 UNSERIALIZE_ARRAY(wsm
, 4);
332 UNSERIALIZE_ARRAY(tba
, 4);
336 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
338 Param
<Addr
> pio_addr
;
339 Param
<Tick
> pio_latency
;
340 SimObjectParam
<Platform
*> platform
;
341 SimObjectParam
<System
*> system
;
342 SimObjectParam
<Tsunami
*> tsunami
;
344 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
346 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
348 INIT_PARAM(pio_addr
, "Device Address"),
349 INIT_PARAM(pio_latency
, "Programmed IO latency"),
350 INIT_PARAM(platform
, "platform"),
351 INIT_PARAM(system
, "system object"),
352 INIT_PARAM(tsunami
, "Tsunami")
354 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
356 CREATE_SIM_OBJECT(TsunamiPChip
)
358 TsunamiPChip::Params
*p
= new TsunamiPChip::Params
;
359 p
->name
= getInstanceName();
360 p
->pio_addr
= pio_addr
;
361 p
->pio_delay
= pio_latency
;
362 p
->platform
= platform
;
364 p
->tsunami
= tsunami
;
365 return new TsunamiPChip(p
);
368 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip
)