src/dev/uart8250.cc

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /** @file
  32  * Implements a 8250 UART
  33  */
  34
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/str.hh"        // for to_number
  40 #include "base/trace.hh"
  41 #include "config/the_isa.hh"
  42 #include "debug/Uart.hh"
  43 #include "dev/platform.hh"
  44 #include "dev/terminal.hh"
  45 #include "dev/uart8250.hh"
  46 #include "mem/packet.hh"
  47 #include "mem/packet_access.hh"
  48
  49 using namespace std;
  50 using namespace TheISA;
  51
  52 Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
  53     : uart(u)
  54 {
  55     DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
  56     intrBit = bit;
  57 }
  58
  59 const char *
  60 Uart8250::IntrEvent::description() const
  61 {
  62     return "uart interrupt delay";
  63 }
  64
  65 void
  66 Uart8250::IntrEvent::process()
  67 {
  68     if (intrBit & uart->IER) {
  69        DPRINTF(Uart, "UART InterEvent, interrupting\n");
  70        uart->platform->postConsoleInt();
  71        uart->status |= intrBit;
  72        uart->lastTxInt = curTick();
  73     }
  74     else
  75        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
  76
  77 }
  78
  79 /* The linux serial driver (8250.c about line 1182) loops reading from
  80  * the device until the device reports it has no more data to
  81  * read. After a maximum of 255 iterations the code prints "serial8250
  82  * too much work for irq X," and breaks out of the loop. Since the
  83  * simulated system is so much slower than the actual system, if a
  84  * user is typing on the keyboard it is very easy for them to provide
  85  * input at a fast enough rate to not allow the loop to exit and thus
  86  * the error to be printed. This magic number provides a delay between
  87  * the time the UART receives a character to send to the simulated
  88  * system and the time it actually notifies the system it has a
  89  * character to send to alleviate this problem. --Ali
  90  */
  91 void
  92 Uart8250::IntrEvent::scheduleIntr()
  93 {
  94     static const Tick interval = 225 * SimClock::Int::ns;
  95     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
  96             curTick() + interval);
  97     if (!scheduled())
  98         uart->schedule(this, curTick() + interval);
  99     else
 100         uart->reschedule(this, curTick() + interval);
 101 }
 102
 103
 104 Uart8250::Uart8250(const Params *p)
 105     : Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
 106       txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 107 {
 108     pioSize = 8;
 109 }
 110
 111 Tick
 112 Uart8250::read(PacketPtr pkt)
 113 {
 114     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 115     assert(pkt->getSize() == 1);
 116
 117     Addr daddr = pkt->getAddr() - pioAddr;
 118     pkt->allocate();
 119
 120     DPRINTF(Uart, " read register %#x\n", daddr);
 121
 122     switch (daddr) {
 123         case 0x0:
 124             if (!(LCR & 0x80)) { // read byte
 125                 if (term->dataAvailable())
 126                     pkt->set(term->in());
 127                 else {
 128                     pkt->set((uint8_t)0);
 129                     // A limited amount of these are ok.
 130                     DPRINTF(Uart, "empty read of RX register\n");
 131                 }
 132                 status &= ~RX_INT;
 133                 platform->clearConsoleInt();
 134
 135                 if (term->dataAvailable() && (IER & UART_IER_RDI))
 136                     rxIntrEvent.scheduleIntr();
 137             } else { // dll divisor latch
 138                ;
 139             }
 140             break;
 141         case 0x1:
 142             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 143                 pkt->set(IER);
 144             } else { // DLM divisor latch MSB
 145                 ;
 146             }
 147             break;
 148         case 0x2: // Intr Identification Register (IIR)
 149             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 150
 151             if (status & RX_INT) /* Rx data interrupt has a higher priority */
 152                 pkt->set(IIR_RXID);
 153             else if (status & TX_INT) {
 154                 pkt->set(IIR_TXID);
 155                 //Tx interrupts are cleared on IIR reads
 156                 status &= ~TX_INT;
 157             } else
 158                 pkt->set(IIR_NOPEND);
 159
 160             break;
 161         case 0x3: // Line Control Register (LCR)
 162             pkt->set(LCR);
 163             break;
 164         case 0x4: // Modem Control Register (MCR)
 165             pkt->set(MCR);
 166             break;
 167         case 0x5: // Line Status Register (LSR)
 168             uint8_t lsr;
 169             lsr = 0;
 170             // check if there are any bytes to be read
 171             if (term->dataAvailable())
 172                 lsr = UART_LSR_DR;
 173             lsr |= UART_LSR_TEMT | UART_LSR_THRE;
 174             pkt->set(lsr);
 175             break;
 176         case 0x6: // Modem Status Register (MSR)
 177             pkt->set((uint8_t)0);
 178             break;
 179         case 0x7: // Scratch Register (SCR)
 180             pkt->set((uint8_t)0); // doesn't exist with at 8250.
 181             break;
 182         default:
 183             panic("Tried to access a UART port that doesn't exist\n");
 184             break;
 185     }
 186 /*    uint32_t d32 = *data;
 187     DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
 188 */
 189     pkt->makeAtomicResponse();
 190     return pioDelay;
 191 }
 192
 193 Tick
 194 Uart8250::write(PacketPtr pkt)
 195 {
 196
 197     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 198     assert(pkt->getSize() == 1);
 199
 200     Addr daddr = pkt->getAddr() - pioAddr;
 201
 202     DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
 203
 204     switch (daddr) {
 205         case 0x0:
 206             if (!(LCR & 0x80)) { // write byte
 207                 term->out(pkt->get<uint8_t>());
 208                 platform->clearConsoleInt();
 209                 status &= ~TX_INT;
 210                 if (UART_IER_THRI & IER)
 211                     txIntrEvent.scheduleIntr();
 212             } else { // dll divisor latch
 213                ;
 214             }
 215             break;
 216         case 0x1:
 217             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 218                 IER = pkt->get<uint8_t>();
 219                 if (UART_IER_THRI & IER)
 220                 {
 221                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
 222                     if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
 223                         DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
 224                                 curTick(), lastTxInt);
 225                         txIntrEvent.process();
 226                     } else {
 227                         DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
 228                                 curTick(), lastTxInt);
 229                         txIntrEvent.scheduleIntr();
 230                     }
 231                 }
 232                 else
 233                 {
 234                     DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
 235                     if (txIntrEvent.scheduled())
 236                         deschedule(txIntrEvent);
 237                     if (status & TX_INT)
 238                         platform->clearConsoleInt();
 239                     status &= ~TX_INT;
 240                 }
 241
 242                 if ((UART_IER_RDI & IER) && term->dataAvailable()) {
 243                     DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
 244                     rxIntrEvent.scheduleIntr();
 245                 } else {
 246                     DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
 247                     if (rxIntrEvent.scheduled())
 248                         deschedule(rxIntrEvent);
 249                     if (status & RX_INT)
 250                         platform->clearConsoleInt();
 251                     status &= ~RX_INT;
 252                 }
 253              } else { // DLM divisor latch MSB
 254                 ;
 255             }
 256             break;
 257         case 0x2: // FIFO Control Register (FCR)
 258             break;
 259         case 0x3: // Line Control Register (LCR)
 260             LCR = pkt->get<uint8_t>();
 261             break;
 262         case 0x4: // Modem Control Register (MCR)
 263             if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
 264                     MCR = 0x9A;
 265             break;
 266         case 0x7: // Scratch Register (SCR)
 267             // We are emulating a 8250 so we don't have a scratch reg
 268             break;
 269         default:
 270             panic("Tried to access a UART port that doesn't exist\n");
 271             break;
 272     }
 273     pkt->makeAtomicResponse();
 274     return pioDelay;
 275 }
 276
 277 void
 278 Uart8250::dataAvailable()
 279 {
 280     // if the kernel wants an interrupt when we have data
 281     if (IER & UART_IER_RDI)
 282     {
 283         platform->postConsoleInt();
 284         status |= RX_INT;
 285     }
 286
 287 }
 288
 289 void
 290 Uart8250::addressRanges(AddrRangeList &range_list)
 291 {
 292     assert(pioSize != 0);
 293     range_list.clear();
 294     range_list.push_back(RangeSize(pioAddr, pioSize));
 295 }
 296
 297
 298
 299 void
 300 Uart8250::serialize(ostream &os)
 301 {
 302     SERIALIZE_SCALAR(status);
 303     SERIALIZE_SCALAR(IER);
 304     SERIALIZE_SCALAR(DLAB);
 305     SERIALIZE_SCALAR(LCR);
 306     SERIALIZE_SCALAR(MCR);
 307     Tick rxintrwhen;
 308     if (rxIntrEvent.scheduled())
 309         rxintrwhen = rxIntrEvent.when();
 310     else
 311         rxintrwhen = 0;
 312     Tick txintrwhen;
 313     if (txIntrEvent.scheduled())
 314         txintrwhen = txIntrEvent.when();
 315     else
 316         txintrwhen = 0;
 317      SERIALIZE_SCALAR(rxintrwhen);
 318      SERIALIZE_SCALAR(txintrwhen);
 319 }
 320
 321 void
 322 Uart8250::unserialize(Checkpoint *cp, const std::string &section)
 323 {
 324     UNSERIALIZE_SCALAR(status);
 325     UNSERIALIZE_SCALAR(IER);
 326     UNSERIALIZE_SCALAR(DLAB);
 327     UNSERIALIZE_SCALAR(LCR);
 328     UNSERIALIZE_SCALAR(MCR);
 329     Tick rxintrwhen;
 330     Tick txintrwhen;
 331     UNSERIALIZE_SCALAR(rxintrwhen);
 332     UNSERIALIZE_SCALAR(txintrwhen);
 333     if (rxintrwhen != 0)
 334         schedule(rxIntrEvent, rxintrwhen);
 335     if (txintrwhen != 0)
 336         schedule(txIntrEvent, txintrwhen);
 337 }
 338
 339 Uart8250 *
 340 Uart8250Params::create()
 341 {
 342     return new Uart8250(this);
 343 }