src/dev/uart8250.cc

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Implements a 8250 UART
  31  */
  32
  33 #include <string>
  34 #include <vector>
  35
  36 #include "arch/alpha/ev5.hh"
  37 #include "base/inifile.hh"
  38 #include "base/str.hh"        // for to_number
  39 #include "base/trace.hh"
  40 #include "dev/simconsole.hh"
  41 #include "dev/uart8250.hh"
  42 #include "dev/platform.hh"
  43 #include "sim/builder.hh"
  44
  45 using namespace std;
  46 using namespace TheISA;
  47
  48 Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
  49     : Event(&mainEventQueue), uart(u)
  50 {
  51     DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
  52     intrBit = bit;
  53 }
  54
  55 const char *
  56 Uart8250::IntrEvent::description()
  57 {
  58     return "uart interrupt delay event";
  59 }
  60
  61 void
  62 Uart8250::IntrEvent::process()
  63 {
  64     if (intrBit & uart->IER) {
  65        DPRINTF(Uart, "UART InterEvent, interrupting\n");
  66        uart->platform->postConsoleInt();
  67        uart->status |= intrBit;
  68     }
  69     else
  70        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
  71
  72 }
  73
  74 /* The linux serial driver (8250.c about line 1182) loops reading from
  75  * the device until the device reports it has no more data to
  76  * read. After a maximum of 255 iterations the code prints "serial8250
  77  * too much work for irq X," and breaks out of the loop. Since the
  78  * simulated system is so much slower than the actual system, if a
  79  * user is typing on the keyboard it is very easy for them to provide
  80  * input at a fast enough rate to not allow the loop to exit and thus
  81  * the error to be printed. This magic number provides a delay between
  82  * the time the UART receives a character to send to the simulated
  83  * system and the time it actually notifies the system it has a
  84  * character to send to alleviate this problem. --Ali
  85  */
  86 void
  87 Uart8250::IntrEvent::scheduleIntr()
  88 {
  89     static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
  90     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
  91             curTick + interval);
  92     if (!scheduled())
  93         schedule(curTick + interval);
  94     else
  95         reschedule(curTick + interval);
  96 }
  97
  98
  99 Uart8250::Uart8250(Params *p)
 100     : Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 101 {
 102     pioSize = 8;
 103
 104     IER = 0;
 105     DLAB = 0;
 106     LCR = 0;
 107     MCR = 0;
 108 }
 109
 110 Tick
 111 Uart8250::read(Packet *pkt)
 112 {
 113     assert(pkt->result == Packet::Unknown);
 114     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 115     assert(pkt->getSize() == 1);
 116
 117     pkt->time += pioDelay;
 118     Addr daddr = pkt->getAddr() - pioAddr;
 119     pkt->allocate();
 120
 121     DPRINTF(Uart, " read register %#x\n", daddr);
 122
 123     switch (daddr) {
 124         case 0x0:
 125             if (!(LCR & 0x80)) { // read byte
 126                 if (cons->dataAvailable())
 127                     cons->in(*pkt->getPtr<uint8_t>());
 128                 else {
 129                     pkt->set((uint8_t)0);
 130                     // A limited amount of these are ok.
 131                     DPRINTF(Uart, "empty read of RX register\n");
 132                 }
 133                 status &= ~RX_INT;
 134                 platform->clearConsoleInt();
 135
 136                 if (cons->dataAvailable() && (IER & UART_IER_RDI))
 137                     rxIntrEvent.scheduleIntr();
 138             } else { // dll divisor latch
 139                ;
 140             }
 141             break;
 142         case 0x1:
 143             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 144                 pkt->set(IER);
 145             } else { // DLM divisor latch MSB
 146                 ;
 147             }
 148             break;
 149         case 0x2: // Intr Identification Register (IIR)
 150             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 151
 152             if (status & RX_INT) /* Rx data interrupt has a higher priority */
 153                 pkt->set(IIR_RXID);
 154             else if (status & TX_INT)
 155                 pkt->set(IIR_TXID);
 156             else
 157                 pkt->set(IIR_NOPEND);
 158
 159             //Tx interrupts are cleared on IIR reads
 160             status &= ~TX_INT;
 161             break;
 162         case 0x3: // Line Control Register (LCR)
 163             pkt->set(LCR);
 164             break;
 165         case 0x4: // Modem Control Register (MCR)
 166             break;
 167         case 0x5: // Line Status Register (LSR)
 168             uint8_t lsr;
 169             lsr = 0;
 170             // check if there are any bytes to be read
 171             if (cons->dataAvailable())
 172                 lsr = UART_LSR_DR;
 173             lsr |= UART_LSR_TEMT | UART_LSR_THRE;
 174             pkt->set(lsr);
 175             break;
 176         case 0x6: // Modem Status Register (MSR)
 177             pkt->set((uint8_t)0);
 178             break;
 179         case 0x7: // Scratch Register (SCR)
 180             pkt->set((uint8_t)0); // doesn't exist with at 8250.
 181             break;
 182         default:
 183             panic("Tried to access a UART port that doesn't exist\n");
 184             break;
 185     }
 186 /*    uint32_t d32 = *data;
 187     DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
 188 */
 189     pkt->result = Packet::Success;
 190     return pioDelay;
 191 }
 192
 193 Tick
 194 Uart8250::write(Packet *pkt)
 195 {
 196
 197     assert(pkt->result == Packet::Unknown);
 198     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 199     assert(pkt->getSize() == 1);
 200
 201     pkt->time += pioDelay;
 202     Addr daddr = pkt->getAddr() - pioAddr;
 203
 204     DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
 205
 206     switch (daddr) {
 207         case 0x0:
 208             if (!(LCR & 0x80)) { // write byte
 209                 cons->out(pkt->get<uint8_t>());
 210                 platform->clearConsoleInt();
 211                 status &= ~TX_INT;
 212                 if (UART_IER_THRI & IER)
 213                     txIntrEvent.scheduleIntr();
 214             } else { // dll divisor latch
 215                ;
 216             }
 217             break;
 218         case 0x1:
 219             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 220                 IER = pkt->get<uint8_t>();
 221                 if (UART_IER_THRI & IER)
 222                 {
 223                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
 224                     txIntrEvent.scheduleIntr();
 225                 }
 226                 else
 227                 {
 228                     DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
 229                     if (txIntrEvent.scheduled())
 230                         txIntrEvent.deschedule();
 231                     if (status & TX_INT)
 232                         platform->clearConsoleInt();
 233                     status &= ~TX_INT;
 234                 }
 235
 236                 if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
 237                     DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
 238                     rxIntrEvent.scheduleIntr();
 239                 } else {
 240                     DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
 241                     if (rxIntrEvent.scheduled())
 242                         rxIntrEvent.deschedule();
 243                     if (status & RX_INT)
 244                         platform->clearConsoleInt();
 245                     status &= ~RX_INT;
 246                 }
 247              } else { // DLM divisor latch MSB
 248                 ;
 249             }
 250             break;
 251         case 0x2: // FIFO Control Register (FCR)
 252             break;
 253         case 0x3: // Line Control Register (LCR)
 254             LCR = pkt->get<uint8_t>();
 255             break;
 256         case 0x4: // Modem Control Register (MCR)
 257             if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
 258                     MCR = 0x9A;
 259             break;
 260         case 0x7: // Scratch Register (SCR)
 261             // We are emulating a 8250 so we don't have a scratch reg
 262             break;
 263         default:
 264             panic("Tried to access a UART port that doesn't exist\n");
 265             break;
 266     }
 267     pkt->result = Packet::Success;
 268     return pioDelay;
 269 }
 270
 271 void
 272 Uart8250::dataAvailable()
 273 {
 274     // if the kernel wants an interrupt when we have data
 275     if (IER & UART_IER_RDI)
 276     {
 277         platform->postConsoleInt();
 278         status |= RX_INT;
 279     }
 280
 281 }
 282
 283 void
 284 Uart8250::addressRanges(AddrRangeList &range_list)
 285 {
 286     assert(pioSize != 0);
 287     range_list.clear();
 288     range_list.push_back(RangeSize(pioAddr, pioSize));
 289 }
 290
 291
 292
 293 void
 294 Uart8250::serialize(ostream &os)
 295 {
 296     SERIALIZE_SCALAR(status);
 297     SERIALIZE_SCALAR(IER);
 298     SERIALIZE_SCALAR(DLAB);
 299     SERIALIZE_SCALAR(LCR);
 300     SERIALIZE_SCALAR(MCR);
 301     Tick rxintrwhen;
 302     if (rxIntrEvent.scheduled())
 303         rxintrwhen = rxIntrEvent.when();
 304     else
 305         rxintrwhen = 0;
 306     Tick txintrwhen;
 307     if (txIntrEvent.scheduled())
 308         txintrwhen = txIntrEvent.when();
 309     else
 310         txintrwhen = 0;
 311      SERIALIZE_SCALAR(rxintrwhen);
 312      SERIALIZE_SCALAR(txintrwhen);
 313 }
 314
 315 void
 316 Uart8250::unserialize(Checkpoint *cp, const std::string &section)
 317 {
 318     UNSERIALIZE_SCALAR(status);
 319     UNSERIALIZE_SCALAR(IER);
 320     UNSERIALIZE_SCALAR(DLAB);
 321     UNSERIALIZE_SCALAR(LCR);
 322     UNSERIALIZE_SCALAR(MCR);
 323     Tick rxintrwhen;
 324     Tick txintrwhen;
 325     UNSERIALIZE_SCALAR(rxintrwhen);
 326     UNSERIALIZE_SCALAR(txintrwhen);
 327     if (rxintrwhen != 0)
 328         rxIntrEvent.schedule(rxintrwhen);
 329     if (txintrwhen != 0)
 330         txIntrEvent.schedule(txintrwhen);
 331 }
 332
 333 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 334
 335     Param<Addr> pio_addr;
 336     Param<Tick> pio_latency;
 337     SimObjectParam<Platform *> platform;
 338     SimObjectParam<SimConsole *> sim_console;
 339     SimObjectParam<System *> system;
 340
 341 END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 342
 343 BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
 344
 345     INIT_PARAM(pio_addr, "Device Address"),
 346     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
 347     INIT_PARAM(platform, "platform"),
 348     INIT_PARAM(sim_console, "The Simulator Console"),
 349     INIT_PARAM(system, "system object")
 350
 351 END_INIT_SIM_OBJECT_PARAMS(Uart8250)
 352
 353 CREATE_SIM_OBJECT(Uart8250)
 354 {
 355     Uart8250::Params *p = new Uart8250::Params;
 356     p->name = getInstanceName();
 357     p->pio_addr = pio_addr;
 358     p->pio_delay = pio_latency;
 359     p->platform = platform;
 360     p->cons = sim_console;
 361     p->system = system;
 362     return new Uart8250(p);
 363 }
 364
 365 REGISTER_SIM_OBJECT("Uart8250", Uart8250)
 366