src/dev/uart8250.cc

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /** @file
  32  * Implements a 8250 UART
  33  */
  34
  35 #include <string>
  36 #include <vector>
  37
  38 #include "arch/alpha/ev5.hh"
  39 #include "base/inifile.hh"
  40 #include "base/str.hh"        // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/simconsole.hh"
  43 #include "dev/uart8250.hh"
  44 #include "dev/platform.hh"
  45 #include "mem/packet.hh"
  46 #include "mem/packet_access.hh"
  47 #include "sim/builder.hh"
  48
  49 using namespace std;
  50 using namespace TheISA;
  51
  52 Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
  53     : Event(&mainEventQueue), uart(u)
  54 {
  55     DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
  56     intrBit = bit;
  57 }
  58
  59 const char *
  60 Uart8250::IntrEvent::description()
  61 {
  62     return "uart interrupt delay event";
  63 }
  64
  65 void
  66 Uart8250::IntrEvent::process()
  67 {
  68     if (intrBit & uart->IER) {
  69        DPRINTF(Uart, "UART InterEvent, interrupting\n");
  70        uart->platform->postConsoleInt();
  71        uart->status |= intrBit;
  72     }
  73     else
  74        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
  75
  76 }
  77
  78 /* The linux serial driver (8250.c about line 1182) loops reading from
  79  * the device until the device reports it has no more data to
  80  * read. After a maximum of 255 iterations the code prints "serial8250
  81  * too much work for irq X," and breaks out of the loop. Since the
  82  * simulated system is so much slower than the actual system, if a
  83  * user is typing on the keyboard it is very easy for them to provide
  84  * input at a fast enough rate to not allow the loop to exit and thus
  85  * the error to be printed. This magic number provides a delay between
  86  * the time the UART receives a character to send to the simulated
  87  * system and the time it actually notifies the system it has a
  88  * character to send to alleviate this problem. --Ali
  89  */
  90 void
  91 Uart8250::IntrEvent::scheduleIntr()
  92 {
  93     static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
  94     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
  95             curTick + interval);
  96     if (!scheduled())
  97         schedule(curTick + interval);
  98     else
  99         reschedule(curTick + interval);
 100 }
 101
 102
 103 Uart8250::Uart8250(Params *p)
 104     : Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 105 {
 106     pioSize = 8;
 107
 108     IER = 0;
 109     DLAB = 0;
 110     LCR = 0;
 111     MCR = 0;
 112 }
 113
 114 Tick
 115 Uart8250::read(PacketPtr pkt)
 116 {
 117     assert(pkt->result == Packet::Unknown);
 118     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 119     assert(pkt->getSize() == 1);
 120
 121     Addr daddr = pkt->getAddr() - pioAddr;
 122     pkt->allocate();
 123
 124     DPRINTF(Uart, " read register %#x\n", daddr);
 125
 126     switch (daddr) {
 127         case 0x0:
 128             if (!(LCR & 0x80)) { // read byte
 129                 if (cons->dataAvailable())
 130                     pkt->set(cons->in());
 131                 else {
 132                     pkt->set((uint8_t)0);
 133                     // A limited amount of these are ok.
 134                     DPRINTF(Uart, "empty read of RX register\n");
 135                 }
 136                 status &= ~RX_INT;
 137                 platform->clearConsoleInt();
 138
 139                 if (cons->dataAvailable() && (IER & UART_IER_RDI))
 140                     rxIntrEvent.scheduleIntr();
 141             } else { // dll divisor latch
 142                ;
 143             }
 144             break;
 145         case 0x1:
 146             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 147                 pkt->set(IER);
 148             } else { // DLM divisor latch MSB
 149                 ;
 150             }
 151             break;
 152         case 0x2: // Intr Identification Register (IIR)
 153             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 154
 155             if (status & RX_INT) /* Rx data interrupt has a higher priority */
 156                 pkt->set(IIR_RXID);
 157             else if (status & TX_INT)
 158                 pkt->set(IIR_TXID);
 159             else
 160                 pkt->set(IIR_NOPEND);
 161
 162             //Tx interrupts are cleared on IIR reads
 163             status &= ~TX_INT;
 164             break;
 165         case 0x3: // Line Control Register (LCR)
 166             pkt->set(LCR);
 167             break;
 168         case 0x4: // Modem Control Register (MCR)
 169             break;
 170         case 0x5: // Line Status Register (LSR)
 171             uint8_t lsr;
 172             lsr = 0;
 173             // check if there are any bytes to be read
 174             if (cons->dataAvailable())
 175                 lsr = UART_LSR_DR;
 176             lsr |= UART_LSR_TEMT | UART_LSR_THRE;
 177             pkt->set(lsr);
 178             break;
 179         case 0x6: // Modem Status Register (MSR)
 180             pkt->set((uint8_t)0);
 181             break;
 182         case 0x7: // Scratch Register (SCR)
 183             pkt->set((uint8_t)0); // doesn't exist with at 8250.
 184             break;
 185         default:
 186             panic("Tried to access a UART port that doesn't exist\n");
 187             break;
 188     }
 189 /*    uint32_t d32 = *data;
 190     DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
 191 */
 192     pkt->result = Packet::Success;
 193     return pioDelay;
 194 }
 195
 196 Tick
 197 Uart8250::write(PacketPtr pkt)
 198 {
 199
 200     assert(pkt->result == Packet::Unknown);
 201     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 202     assert(pkt->getSize() == 1);
 203
 204     Addr daddr = pkt->getAddr() - pioAddr;
 205
 206     DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
 207
 208     switch (daddr) {
 209         case 0x0:
 210             if (!(LCR & 0x80)) { // write byte
 211                 cons->out(pkt->get<uint8_t>());
 212                 platform->clearConsoleInt();
 213                 status &= ~TX_INT;
 214                 if (UART_IER_THRI & IER)
 215                     txIntrEvent.scheduleIntr();
 216             } else { // dll divisor latch
 217                ;
 218             }
 219             break;
 220         case 0x1:
 221             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 222                 IER = pkt->get<uint8_t>();
 223                 if (UART_IER_THRI & IER)
 224                 {
 225                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
 226                     txIntrEvent.scheduleIntr();
 227                 }
 228                 else
 229                 {
 230                     DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
 231                     if (txIntrEvent.scheduled())
 232                         txIntrEvent.deschedule();
 233                     if (status & TX_INT)
 234                         platform->clearConsoleInt();
 235                     status &= ~TX_INT;
 236                 }
 237
 238                 if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
 239                     DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
 240                     rxIntrEvent.scheduleIntr();
 241                 } else {
 242                     DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
 243                     if (rxIntrEvent.scheduled())
 244                         rxIntrEvent.deschedule();
 245                     if (status & RX_INT)
 246                         platform->clearConsoleInt();
 247                     status &= ~RX_INT;
 248                 }
 249              } else { // DLM divisor latch MSB
 250                 ;
 251             }
 252             break;
 253         case 0x2: // FIFO Control Register (FCR)
 254             break;
 255         case 0x3: // Line Control Register (LCR)
 256             LCR = pkt->get<uint8_t>();
 257             break;
 258         case 0x4: // Modem Control Register (MCR)
 259             if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
 260                     MCR = 0x9A;
 261             break;
 262         case 0x7: // Scratch Register (SCR)
 263             // We are emulating a 8250 so we don't have a scratch reg
 264             break;
 265         default:
 266             panic("Tried to access a UART port that doesn't exist\n");
 267             break;
 268     }
 269     pkt->result = Packet::Success;
 270     return pioDelay;
 271 }
 272
 273 void
 274 Uart8250::dataAvailable()
 275 {
 276     // if the kernel wants an interrupt when we have data
 277     if (IER & UART_IER_RDI)
 278     {
 279         platform->postConsoleInt();
 280         status |= RX_INT;
 281     }
 282
 283 }
 284
 285 void
 286 Uart8250::addressRanges(AddrRangeList &range_list)
 287 {
 288     assert(pioSize != 0);
 289     range_list.clear();
 290     range_list.push_back(RangeSize(pioAddr, pioSize));
 291 }
 292
 293
 294
 295 void
 296 Uart8250::serialize(ostream &os)
 297 {
 298     SERIALIZE_SCALAR(status);
 299     SERIALIZE_SCALAR(IER);
 300     SERIALIZE_SCALAR(DLAB);
 301     SERIALIZE_SCALAR(LCR);
 302     SERIALIZE_SCALAR(MCR);
 303     Tick rxintrwhen;
 304     if (rxIntrEvent.scheduled())
 305         rxintrwhen = rxIntrEvent.when();
 306     else
 307         rxintrwhen = 0;
 308     Tick txintrwhen;
 309     if (txIntrEvent.scheduled())
 310         txintrwhen = txIntrEvent.when();
 311     else
 312         txintrwhen = 0;
 313      SERIALIZE_SCALAR(rxintrwhen);
 314      SERIALIZE_SCALAR(txintrwhen);
 315 }
 316
 317 void
 318 Uart8250::unserialize(Checkpoint *cp, const std::string &section)
 319 {
 320     UNSERIALIZE_SCALAR(status);
 321     UNSERIALIZE_SCALAR(IER);
 322     UNSERIALIZE_SCALAR(DLAB);
 323     UNSERIALIZE_SCALAR(LCR);
 324     UNSERIALIZE_SCALAR(MCR);
 325     Tick rxintrwhen;
 326     Tick txintrwhen;
 327     UNSERIALIZE_SCALAR(rxintrwhen);
 328     UNSERIALIZE_SCALAR(txintrwhen);
 329     if (rxintrwhen != 0)
 330         rxIntrEvent.schedule(rxintrwhen);
 331     if (txintrwhen != 0)
 332         txIntrEvent.schedule(txintrwhen);
 333 }
 334
 335 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 336
 337     Param<Addr> pio_addr;
 338     Param<Tick> pio_latency;
 339     SimObjectParam<Platform *> platform;
 340     SimObjectParam<SimConsole *> sim_console;
 341     SimObjectParam<System *> system;
 342
 343 END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 344
 345 BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
 346
 347     INIT_PARAM(pio_addr, "Device Address"),
 348     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
 349     INIT_PARAM(platform, "platform"),
 350     INIT_PARAM(sim_console, "The Simulator Console"),
 351     INIT_PARAM(system, "system object")
 352
 353 END_INIT_SIM_OBJECT_PARAMS(Uart8250)
 354
 355 CREATE_SIM_OBJECT(Uart8250)
 356 {
 357     Uart8250::Params *p = new Uart8250::Params;
 358     p->name = getInstanceName();
 359     p->pio_addr = pio_addr;
 360     p->pio_delay = pio_latency;
 361     p->platform = platform;
 362     p->cons = sim_console;
 363     p->system = system;
 364     return new Uart8250(p);
 365 }
 366
 367 REGISTER_SIM_OBJECT("Uart8250", Uart8250)
 368