2 * Copyright (c) 2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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32 * Implements a 8250 UART
38 #include "base/inifile.hh"
39 #include "base/str.hh" // for to_number
40 #include "base/trace.hh"
41 #include "dev/platform.hh"
42 #include "dev/terminal.hh"
43 #include "dev/uart8250.hh"
44 #include "mem/packet.hh"
45 #include "mem/packet_access.hh"
48 using namespace TheISA
;
50 Uart8250::IntrEvent::IntrEvent(Uart8250
*u
, int bit
)
53 DPRINTF(Uart
, "UART Interrupt Event Initilizing\n");
58 Uart8250::IntrEvent::description() const
60 return "uart interrupt delay";
64 Uart8250::IntrEvent::process()
66 if (intrBit
& uart
->IER
) {
67 DPRINTF(Uart
, "UART InterEvent, interrupting\n");
68 uart
->platform
->postConsoleInt();
69 uart
->status
|= intrBit
;
70 uart
->lastTxInt
= curTick
;
73 DPRINTF(Uart
, "UART InterEvent, not interrupting\n");
77 /* The linux serial driver (8250.c about line 1182) loops reading from
78 * the device until the device reports it has no more data to
79 * read. After a maximum of 255 iterations the code prints "serial8250
80 * too much work for irq X," and breaks out of the loop. Since the
81 * simulated system is so much slower than the actual system, if a
82 * user is typing on the keyboard it is very easy for them to provide
83 * input at a fast enough rate to not allow the loop to exit and thus
84 * the error to be printed. This magic number provides a delay between
85 * the time the UART receives a character to send to the simulated
86 * system and the time it actually notifies the system it has a
87 * character to send to alleviate this problem. --Ali
90 Uart8250::IntrEvent::scheduleIntr()
92 static const Tick interval
= (Tick
)((Clock::Float::s
/ 2e9
) * 450);
93 DPRINTF(Uart
, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit
,
96 uart
->schedule(this, curTick
+ interval
);
98 uart
->reschedule(this, curTick
+ interval
);
102 Uart8250::Uart8250(const Params
*p
)
103 : Uart(p
), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
104 txIntrEvent(this, TX_INT
), rxIntrEvent(this, RX_INT
)
110 Uart8250::read(PacketPtr pkt
)
112 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
113 assert(pkt
->getSize() == 1);
115 Addr daddr
= pkt
->getAddr() - pioAddr
;
118 DPRINTF(Uart
, " read register %#x\n", daddr
);
122 if (!(LCR
& 0x80)) { // read byte
123 if (term
->dataAvailable())
124 pkt
->set(term
->in());
126 pkt
->set((uint8_t)0);
127 // A limited amount of these are ok.
128 DPRINTF(Uart
, "empty read of RX register\n");
131 platform
->clearConsoleInt();
133 if (term
->dataAvailable() && (IER
& UART_IER_RDI
))
134 rxIntrEvent
.scheduleIntr();
135 } else { // dll divisor latch
140 if (!(LCR
& 0x80)) { // Intr Enable Register(IER)
142 } else { // DLM divisor latch MSB
146 case 0x2: // Intr Identification Register (IIR)
147 DPRINTF(Uart
, "IIR Read, status = %#x\n", (uint32_t)status
);
149 if (status
& RX_INT
) /* Rx data interrupt has a higher priority */
151 else if (status
& TX_INT
) {
153 //Tx interrupts are cleared on IIR reads
156 pkt
->set(IIR_NOPEND
);
159 case 0x3: // Line Control Register (LCR)
162 case 0x4: // Modem Control Register (MCR)
164 case 0x5: // Line Status Register (LSR)
167 // check if there are any bytes to be read
168 if (term
->dataAvailable())
170 lsr
|= UART_LSR_TEMT
| UART_LSR_THRE
;
173 case 0x6: // Modem Status Register (MSR)
174 pkt
->set((uint8_t)0);
176 case 0x7: // Scratch Register (SCR)
177 pkt
->set((uint8_t)0); // doesn't exist with at 8250.
180 panic("Tried to access a UART port that doesn't exist\n");
183 /* uint32_t d32 = *data;
184 DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
186 pkt
->makeAtomicResponse();
191 Uart8250::write(PacketPtr pkt
)
194 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
195 assert(pkt
->getSize() == 1);
197 Addr daddr
= pkt
->getAddr() - pioAddr
;
199 DPRINTF(Uart
, " write register %#x value %#x\n", daddr
, pkt
->get
<uint8_t>());
203 if (!(LCR
& 0x80)) { // write byte
204 term
->out(pkt
->get
<uint8_t>());
205 platform
->clearConsoleInt();
207 if (UART_IER_THRI
& IER
)
208 txIntrEvent
.scheduleIntr();
209 } else { // dll divisor latch
214 if (!(LCR
& 0x80)) { // Intr Enable Register(IER)
215 IER
= pkt
->get
<uint8_t>();
216 if (UART_IER_THRI
& IER
)
218 DPRINTF(Uart
, "IER: IER_THRI set, scheduling TX intrrupt\n");
219 if (curTick
- lastTxInt
>
220 (Tick
)((Clock::Float::s
/ 2e9
) * 450)) {
221 DPRINTF(Uart
, "-- Interrupting Immediately... %d,%d\n",
223 txIntrEvent
.process();
225 DPRINTF(Uart
, "-- Delaying interrupt... %d,%d\n",
227 txIntrEvent
.scheduleIntr();
232 DPRINTF(Uart
, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
233 if (txIntrEvent
.scheduled())
234 deschedule(txIntrEvent
);
236 platform
->clearConsoleInt();
240 if ((UART_IER_RDI
& IER
) && term
->dataAvailable()) {
241 DPRINTF(Uart
, "IER: IER_RDI set, scheduling RX intrrupt\n");
242 rxIntrEvent
.scheduleIntr();
244 DPRINTF(Uart
, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
245 if (rxIntrEvent
.scheduled())
246 deschedule(rxIntrEvent
);
248 platform
->clearConsoleInt();
251 } else { // DLM divisor latch MSB
255 case 0x2: // FIFO Control Register (FCR)
257 case 0x3: // Line Control Register (LCR)
258 LCR
= pkt
->get
<uint8_t>();
260 case 0x4: // Modem Control Register (MCR)
261 if (pkt
->get
<uint8_t>() == (UART_MCR_LOOP
| 0x0A))
264 case 0x7: // Scratch Register (SCR)
265 // We are emulating a 8250 so we don't have a scratch reg
268 panic("Tried to access a UART port that doesn't exist\n");
271 pkt
->makeAtomicResponse();
276 Uart8250::dataAvailable()
278 // if the kernel wants an interrupt when we have data
279 if (IER
& UART_IER_RDI
)
281 platform
->postConsoleInt();
288 Uart8250::addressRanges(AddrRangeList
&range_list
)
290 assert(pioSize
!= 0);
292 range_list
.push_back(RangeSize(pioAddr
, pioSize
));
298 Uart8250::serialize(ostream
&os
)
300 SERIALIZE_SCALAR(status
);
301 SERIALIZE_SCALAR(IER
);
302 SERIALIZE_SCALAR(DLAB
);
303 SERIALIZE_SCALAR(LCR
);
304 SERIALIZE_SCALAR(MCR
);
306 if (rxIntrEvent
.scheduled())
307 rxintrwhen
= rxIntrEvent
.when();
311 if (txIntrEvent
.scheduled())
312 txintrwhen
= txIntrEvent
.when();
315 SERIALIZE_SCALAR(rxintrwhen
);
316 SERIALIZE_SCALAR(txintrwhen
);
320 Uart8250::unserialize(Checkpoint
*cp
, const std::string
§ion
)
322 UNSERIALIZE_SCALAR(status
);
323 UNSERIALIZE_SCALAR(IER
);
324 UNSERIALIZE_SCALAR(DLAB
);
325 UNSERIALIZE_SCALAR(LCR
);
326 UNSERIALIZE_SCALAR(MCR
);
329 UNSERIALIZE_SCALAR(rxintrwhen
);
330 UNSERIALIZE_SCALAR(txintrwhen
);
332 schedule(rxIntrEvent
, rxintrwhen
);
334 schedule(txIntrEvent
, txintrwhen
);
338 Uart8250Params::create()
340 return new Uart8250(this);