9465eca57ea3ffb93074b765b70634b770707d7b
2 * Copyright (c) 2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Implements a 8250 UART
38 #include "base/inifile.hh"
39 #include "base/str.hh" // for to_number
40 #include "base/trace.hh"
41 #include "dev/simconsole.hh"
42 #include "dev/uart8250.hh"
43 #include "dev/platform.hh"
44 #include "mem/packet.hh"
45 #include "mem/packet_access.hh"
48 using namespace TheISA
;
50 Uart8250::IntrEvent::IntrEvent(Uart8250
*u
, int bit
)
51 : Event(&mainEventQueue
), uart(u
)
53 DPRINTF(Uart
, "UART Interrupt Event Initilizing\n");
58 Uart8250::IntrEvent::description()
60 return "uart interrupt delay event";
64 Uart8250::IntrEvent::process()
66 if (intrBit
& uart
->IER
) {
67 DPRINTF(Uart
, "UART InterEvent, interrupting\n");
68 uart
->platform
->postConsoleInt();
69 uart
->status
|= intrBit
;
70 uart
->lastTxInt
= curTick
;
73 DPRINTF(Uart
, "UART InterEvent, not interrupting\n");
77 /* The linux serial driver (8250.c about line 1182) loops reading from
78 * the device until the device reports it has no more data to
79 * read. After a maximum of 255 iterations the code prints "serial8250
80 * too much work for irq X," and breaks out of the loop. Since the
81 * simulated system is so much slower than the actual system, if a
82 * user is typing on the keyboard it is very easy for them to provide
83 * input at a fast enough rate to not allow the loop to exit and thus
84 * the error to be printed. This magic number provides a delay between
85 * the time the UART receives a character to send to the simulated
86 * system and the time it actually notifies the system it has a
87 * character to send to alleviate this problem. --Ali
90 Uart8250::IntrEvent::scheduleIntr()
92 static const Tick interval
= (Tick
)((Clock::Float::s
/ 2e9
) * 450);
93 DPRINTF(Uart
, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit
,
96 schedule(curTick
+ interval
);
98 reschedule(curTick
+ interval
);
102 Uart8250::Uart8250(const Params
*p
)
103 : Uart(p
), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
104 txIntrEvent(this, TX_INT
), rxIntrEvent(this, RX_INT
)
110 Uart8250::read(PacketPtr pkt
)
112 assert(pkt
->result
== Packet::Unknown
);
113 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
114 assert(pkt
->getSize() == 1);
116 Addr daddr
= pkt
->getAddr() - pioAddr
;
119 DPRINTF(Uart
, " read register %#x\n", daddr
);
123 if (!(LCR
& 0x80)) { // read byte
124 if (cons
->dataAvailable())
125 pkt
->set(cons
->in());
127 pkt
->set((uint8_t)0);
128 // A limited amount of these are ok.
129 DPRINTF(Uart
, "empty read of RX register\n");
132 platform
->clearConsoleInt();
134 if (cons
->dataAvailable() && (IER
& UART_IER_RDI
))
135 rxIntrEvent
.scheduleIntr();
136 } else { // dll divisor latch
141 if (!(LCR
& 0x80)) { // Intr Enable Register(IER)
143 } else { // DLM divisor latch MSB
147 case 0x2: // Intr Identification Register (IIR)
148 DPRINTF(Uart
, "IIR Read, status = %#x\n", (uint32_t)status
);
150 if (status
& RX_INT
) /* Rx data interrupt has a higher priority */
152 else if (status
& TX_INT
) {
154 //Tx interrupts are cleared on IIR reads
157 pkt
->set(IIR_NOPEND
);
160 case 0x3: // Line Control Register (LCR)
163 case 0x4: // Modem Control Register (MCR)
165 case 0x5: // Line Status Register (LSR)
168 // check if there are any bytes to be read
169 if (cons
->dataAvailable())
171 lsr
|= UART_LSR_TEMT
| UART_LSR_THRE
;
174 case 0x6: // Modem Status Register (MSR)
175 pkt
->set((uint8_t)0);
177 case 0x7: // Scratch Register (SCR)
178 pkt
->set((uint8_t)0); // doesn't exist with at 8250.
181 panic("Tried to access a UART port that doesn't exist\n");
184 /* uint32_t d32 = *data;
185 DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
187 pkt
->result
= Packet::Success
;
192 Uart8250::write(PacketPtr pkt
)
195 assert(pkt
->result
== Packet::Unknown
);
196 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
197 assert(pkt
->getSize() == 1);
199 Addr daddr
= pkt
->getAddr() - pioAddr
;
201 DPRINTF(Uart
, " write register %#x value %#x\n", daddr
, pkt
->get
<uint8_t>());
205 if (!(LCR
& 0x80)) { // write byte
206 cons
->out(pkt
->get
<uint8_t>());
207 platform
->clearConsoleInt();
209 if (UART_IER_THRI
& IER
)
210 txIntrEvent
.scheduleIntr();
211 } else { // dll divisor latch
216 if (!(LCR
& 0x80)) { // Intr Enable Register(IER)
217 IER
= pkt
->get
<uint8_t>();
218 if (UART_IER_THRI
& IER
)
220 DPRINTF(Uart
, "IER: IER_THRI set, scheduling TX intrrupt\n");
221 if (curTick
- lastTxInt
>
222 (Tick
)((Clock::Float::s
/ 2e9
) * 450)) {
223 DPRINTF(Uart
, "-- Interrupting Immediately... %d,%d\n",
225 txIntrEvent
.process();
227 DPRINTF(Uart
, "-- Delaying interrupt... %d,%d\n",
229 txIntrEvent
.scheduleIntr();
234 DPRINTF(Uart
, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
235 if (txIntrEvent
.scheduled())
236 txIntrEvent
.deschedule();
238 platform
->clearConsoleInt();
242 if ((UART_IER_RDI
& IER
) && cons
->dataAvailable()) {
243 DPRINTF(Uart
, "IER: IER_RDI set, scheduling RX intrrupt\n");
244 rxIntrEvent
.scheduleIntr();
246 DPRINTF(Uart
, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
247 if (rxIntrEvent
.scheduled())
248 rxIntrEvent
.deschedule();
250 platform
->clearConsoleInt();
253 } else { // DLM divisor latch MSB
257 case 0x2: // FIFO Control Register (FCR)
259 case 0x3: // Line Control Register (LCR)
260 LCR
= pkt
->get
<uint8_t>();
262 case 0x4: // Modem Control Register (MCR)
263 if (pkt
->get
<uint8_t>() == (UART_MCR_LOOP
| 0x0A))
266 case 0x7: // Scratch Register (SCR)
267 // We are emulating a 8250 so we don't have a scratch reg
270 panic("Tried to access a UART port that doesn't exist\n");
273 pkt
->result
= Packet::Success
;
278 Uart8250::dataAvailable()
280 // if the kernel wants an interrupt when we have data
281 if (IER
& UART_IER_RDI
)
283 platform
->postConsoleInt();
290 Uart8250::addressRanges(AddrRangeList
&range_list
)
292 assert(pioSize
!= 0);
294 range_list
.push_back(RangeSize(pioAddr
, pioSize
));
300 Uart8250::serialize(ostream
&os
)
302 SERIALIZE_SCALAR(status
);
303 SERIALIZE_SCALAR(IER
);
304 SERIALIZE_SCALAR(DLAB
);
305 SERIALIZE_SCALAR(LCR
);
306 SERIALIZE_SCALAR(MCR
);
308 if (rxIntrEvent
.scheduled())
309 rxintrwhen
= rxIntrEvent
.when();
313 if (txIntrEvent
.scheduled())
314 txintrwhen
= txIntrEvent
.when();
317 SERIALIZE_SCALAR(rxintrwhen
);
318 SERIALIZE_SCALAR(txintrwhen
);
322 Uart8250::unserialize(Checkpoint
*cp
, const std::string
§ion
)
324 UNSERIALIZE_SCALAR(status
);
325 UNSERIALIZE_SCALAR(IER
);
326 UNSERIALIZE_SCALAR(DLAB
);
327 UNSERIALIZE_SCALAR(LCR
);
328 UNSERIALIZE_SCALAR(MCR
);
331 UNSERIALIZE_SCALAR(rxintrwhen
);
332 UNSERIALIZE_SCALAR(txintrwhen
);
334 rxIntrEvent
.schedule(rxintrwhen
);
336 txIntrEvent
.schedule(txintrwhen
);
340 Uart8250Params::create()
342 return new Uart8250(this);