2 * Copyright (c) 2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Implements a 8250 UART
38 #include "arch/alpha/ev5.hh"
39 #include "base/inifile.hh"
40 #include "base/str.hh" // for to_number
41 #include "base/trace.hh"
42 #include "dev/simconsole.hh"
43 #include "dev/uart8250.hh"
44 #include "dev/platform.hh"
45 #include "sim/builder.hh"
48 using namespace TheISA
;
50 Uart8250::IntrEvent::IntrEvent(Uart8250
*u
, int bit
)
51 : Event(&mainEventQueue
), uart(u
)
53 DPRINTF(Uart
, "UART Interrupt Event Initilizing\n");
58 Uart8250::IntrEvent::description()
60 return "uart interrupt delay event";
64 Uart8250::IntrEvent::process()
66 if (intrBit
& uart
->IER
) {
67 DPRINTF(Uart
, "UART InterEvent, interrupting\n");
68 uart
->platform
->postConsoleInt();
69 uart
->status
|= intrBit
;
72 DPRINTF(Uart
, "UART InterEvent, not interrupting\n");
76 /* The linux serial driver (8250.c about line 1182) loops reading from
77 * the device until the device reports it has no more data to
78 * read. After a maximum of 255 iterations the code prints "serial8250
79 * too much work for irq X," and breaks out of the loop. Since the
80 * simulated system is so much slower than the actual system, if a
81 * user is typing on the keyboard it is very easy for them to provide
82 * input at a fast enough rate to not allow the loop to exit and thus
83 * the error to be printed. This magic number provides a delay between
84 * the time the UART receives a character to send to the simulated
85 * system and the time it actually notifies the system it has a
86 * character to send to alleviate this problem. --Ali
89 Uart8250::IntrEvent::scheduleIntr()
91 static const Tick interval
= (Tick
)((Clock::Float::s
/ 2e9
) * 450);
92 DPRINTF(Uart
, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit
,
95 schedule(curTick
+ interval
);
97 reschedule(curTick
+ interval
);
101 Uart8250::Uart8250(Params
*p
)
102 : Uart(p
), txIntrEvent(this, TX_INT
), rxIntrEvent(this, RX_INT
)
113 Uart8250::read(Packet
*pkt
)
115 assert(pkt
->result
== Packet::Unknown
);
116 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
117 assert(pkt
->getSize() == 1);
119 Addr daddr
= pkt
->getAddr() - pioAddr
;
122 DPRINTF(Uart
, " read register %#x\n", daddr
);
126 if (!(LCR
& 0x80)) { // read byte
127 if (cons
->dataAvailable())
128 pkt
->set(cons
->in());
130 pkt
->set((uint8_t)0);
131 // A limited amount of these are ok.
132 DPRINTF(Uart
, "empty read of RX register\n");
135 platform
->clearConsoleInt();
137 if (cons
->dataAvailable() && (IER
& UART_IER_RDI
))
138 rxIntrEvent
.scheduleIntr();
139 } else { // dll divisor latch
144 if (!(LCR
& 0x80)) { // Intr Enable Register(IER)
146 } else { // DLM divisor latch MSB
150 case 0x2: // Intr Identification Register (IIR)
151 DPRINTF(Uart
, "IIR Read, status = %#x\n", (uint32_t)status
);
153 if (status
& RX_INT
) /* Rx data interrupt has a higher priority */
155 else if (status
& TX_INT
)
158 pkt
->set(IIR_NOPEND
);
160 //Tx interrupts are cleared on IIR reads
163 case 0x3: // Line Control Register (LCR)
166 case 0x4: // Modem Control Register (MCR)
168 case 0x5: // Line Status Register (LSR)
171 // check if there are any bytes to be read
172 if (cons
->dataAvailable())
174 lsr
|= UART_LSR_TEMT
| UART_LSR_THRE
;
177 case 0x6: // Modem Status Register (MSR)
178 pkt
->set((uint8_t)0);
180 case 0x7: // Scratch Register (SCR)
181 pkt
->set((uint8_t)0); // doesn't exist with at 8250.
184 panic("Tried to access a UART port that doesn't exist\n");
187 /* uint32_t d32 = *data;
188 DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
190 pkt
->result
= Packet::Success
;
195 Uart8250::write(Packet
*pkt
)
198 assert(pkt
->result
== Packet::Unknown
);
199 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
200 assert(pkt
->getSize() == 1);
202 Addr daddr
= pkt
->getAddr() - pioAddr
;
204 DPRINTF(Uart
, " write register %#x value %#x\n", daddr
, pkt
->get
<uint8_t>());
208 if (!(LCR
& 0x80)) { // write byte
209 cons
->out(pkt
->get
<uint8_t>());
210 platform
->clearConsoleInt();
212 if (UART_IER_THRI
& IER
)
213 txIntrEvent
.scheduleIntr();
214 } else { // dll divisor latch
219 if (!(LCR
& 0x80)) { // Intr Enable Register(IER)
220 IER
= pkt
->get
<uint8_t>();
221 if (UART_IER_THRI
& IER
)
223 DPRINTF(Uart
, "IER: IER_THRI set, scheduling TX intrrupt\n");
224 txIntrEvent
.scheduleIntr();
228 DPRINTF(Uart
, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
229 if (txIntrEvent
.scheduled())
230 txIntrEvent
.deschedule();
232 platform
->clearConsoleInt();
236 if ((UART_IER_RDI
& IER
) && cons
->dataAvailable()) {
237 DPRINTF(Uart
, "IER: IER_RDI set, scheduling RX intrrupt\n");
238 rxIntrEvent
.scheduleIntr();
240 DPRINTF(Uart
, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
241 if (rxIntrEvent
.scheduled())
242 rxIntrEvent
.deschedule();
244 platform
->clearConsoleInt();
247 } else { // DLM divisor latch MSB
251 case 0x2: // FIFO Control Register (FCR)
253 case 0x3: // Line Control Register (LCR)
254 LCR
= pkt
->get
<uint8_t>();
256 case 0x4: // Modem Control Register (MCR)
257 if (pkt
->get
<uint8_t>() == (UART_MCR_LOOP
| 0x0A))
260 case 0x7: // Scratch Register (SCR)
261 // We are emulating a 8250 so we don't have a scratch reg
264 panic("Tried to access a UART port that doesn't exist\n");
267 pkt
->result
= Packet::Success
;
272 Uart8250::dataAvailable()
274 // if the kernel wants an interrupt when we have data
275 if (IER
& UART_IER_RDI
)
277 platform
->postConsoleInt();
284 Uart8250::addressRanges(AddrRangeList
&range_list
)
286 assert(pioSize
!= 0);
288 range_list
.push_back(RangeSize(pioAddr
, pioSize
));
294 Uart8250::serialize(ostream
&os
)
296 SERIALIZE_SCALAR(status
);
297 SERIALIZE_SCALAR(IER
);
298 SERIALIZE_SCALAR(DLAB
);
299 SERIALIZE_SCALAR(LCR
);
300 SERIALIZE_SCALAR(MCR
);
302 if (rxIntrEvent
.scheduled())
303 rxintrwhen
= rxIntrEvent
.when();
307 if (txIntrEvent
.scheduled())
308 txintrwhen
= txIntrEvent
.when();
311 SERIALIZE_SCALAR(rxintrwhen
);
312 SERIALIZE_SCALAR(txintrwhen
);
316 Uart8250::unserialize(Checkpoint
*cp
, const std::string
§ion
)
318 UNSERIALIZE_SCALAR(status
);
319 UNSERIALIZE_SCALAR(IER
);
320 UNSERIALIZE_SCALAR(DLAB
);
321 UNSERIALIZE_SCALAR(LCR
);
322 UNSERIALIZE_SCALAR(MCR
);
325 UNSERIALIZE_SCALAR(rxintrwhen
);
326 UNSERIALIZE_SCALAR(txintrwhen
);
328 rxIntrEvent
.schedule(rxintrwhen
);
330 txIntrEvent
.schedule(txintrwhen
);
333 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250
)
335 Param
<Addr
> pio_addr
;
336 Param
<Tick
> pio_latency
;
337 SimObjectParam
<Platform
*> platform
;
338 SimObjectParam
<SimConsole
*> sim_console
;
339 SimObjectParam
<System
*> system
;
341 END_DECLARE_SIM_OBJECT_PARAMS(Uart8250
)
343 BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250
)
345 INIT_PARAM(pio_addr
, "Device Address"),
346 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency", 1000),
347 INIT_PARAM(platform
, "platform"),
348 INIT_PARAM(sim_console
, "The Simulator Console"),
349 INIT_PARAM(system
, "system object")
351 END_INIT_SIM_OBJECT_PARAMS(Uart8250
)
353 CREATE_SIM_OBJECT(Uart8250
)
355 Uart8250::Params
*p
= new Uart8250::Params
;
356 p
->name
= getInstanceName();
357 p
->pio_addr
= pio_addr
;
358 p
->pio_delay
= pio_latency
;
359 p
->platform
= platform
;
360 p
->cons
= sim_console
;
362 return new Uart8250(p
);
365 REGISTER_SIM_OBJECT("Uart8250", Uart8250
)