src/dev/uart8250.cc

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /** @file
  32  * Implements a 8250 UART
  33  */
  34
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/str.hh"        // for to_number
  40 #include "base/trace.hh"
  41 #include "dev/simconsole.hh"
  42 #include "dev/uart8250.hh"
  43 #include "dev/platform.hh"
  44 #include "mem/packet.hh"
  45 #include "mem/packet_access.hh"
  46 #include "sim/builder.hh"
  47
  48 using namespace std;
  49 using namespace TheISA;
  50
  51 Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
  52     : Event(&mainEventQueue), uart(u)
  53 {
  54     DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
  55     intrBit = bit;
  56 }
  57
  58 const char *
  59 Uart8250::IntrEvent::description()
  60 {
  61     return "uart interrupt delay event";
  62 }
  63
  64 void
  65 Uart8250::IntrEvent::process()
  66 {
  67     if (intrBit & uart->IER) {
  68        DPRINTF(Uart, "UART InterEvent, interrupting\n");
  69        uart->platform->postConsoleInt();
  70        uart->status |= intrBit;
  71     }
  72     else
  73        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
  74
  75 }
  76
  77 /* The linux serial driver (8250.c about line 1182) loops reading from
  78  * the device until the device reports it has no more data to
  79  * read. After a maximum of 255 iterations the code prints "serial8250
  80  * too much work for irq X," and breaks out of the loop. Since the
  81  * simulated system is so much slower than the actual system, if a
  82  * user is typing on the keyboard it is very easy for them to provide
  83  * input at a fast enough rate to not allow the loop to exit and thus
  84  * the error to be printed. This magic number provides a delay between
  85  * the time the UART receives a character to send to the simulated
  86  * system and the time it actually notifies the system it has a
  87  * character to send to alleviate this problem. --Ali
  88  */
  89 void
  90 Uart8250::IntrEvent::scheduleIntr()
  91 {
  92     static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
  93     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
  94             curTick + interval);
  95     if (!scheduled())
  96         schedule(curTick + interval);
  97     else
  98         reschedule(curTick + interval);
  99 }
 100
 101
 102 Uart8250::Uart8250(Params *p)
 103     : Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 104 {
 105     pioSize = 8;
 106
 107     IER = 0;
 108     DLAB = 0;
 109     LCR = 0;
 110     MCR = 0;
 111 }
 112
 113 Tick
 114 Uart8250::read(PacketPtr pkt)
 115 {
 116     assert(pkt->result == Packet::Unknown);
 117     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 118     assert(pkt->getSize() == 1);
 119
 120     Addr daddr = pkt->getAddr() - pioAddr;
 121     pkt->allocate();
 122
 123     DPRINTF(Uart, " read register %#x\n", daddr);
 124
 125     switch (daddr) {
 126         case 0x0:
 127             if (!(LCR & 0x80)) { // read byte
 128                 if (cons->dataAvailable())
 129                     pkt->set(cons->in());
 130                 else {
 131                     pkt->set((uint8_t)0);
 132                     // A limited amount of these are ok.
 133                     DPRINTF(Uart, "empty read of RX register\n");
 134                 }
 135                 status &= ~RX_INT;
 136                 platform->clearConsoleInt();
 137
 138                 if (cons->dataAvailable() && (IER & UART_IER_RDI))
 139                     rxIntrEvent.scheduleIntr();
 140             } else { // dll divisor latch
 141                ;
 142             }
 143             break;
 144         case 0x1:
 145             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 146                 pkt->set(IER);
 147             } else { // DLM divisor latch MSB
 148                 ;
 149             }
 150             break;
 151         case 0x2: // Intr Identification Register (IIR)
 152             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 153
 154             if (status & RX_INT) /* Rx data interrupt has a higher priority */
 155                 pkt->set(IIR_RXID);
 156             else if (status & TX_INT)
 157                 pkt->set(IIR_TXID);
 158             else
 159                 pkt->set(IIR_NOPEND);
 160
 161             //Tx interrupts are cleared on IIR reads
 162             status &= ~TX_INT;
 163             break;
 164         case 0x3: // Line Control Register (LCR)
 165             pkt->set(LCR);
 166             break;
 167         case 0x4: // Modem Control Register (MCR)
 168             break;
 169         case 0x5: // Line Status Register (LSR)
 170             uint8_t lsr;
 171             lsr = 0;
 172             // check if there are any bytes to be read
 173             if (cons->dataAvailable())
 174                 lsr = UART_LSR_DR;
 175             lsr |= UART_LSR_TEMT | UART_LSR_THRE;
 176             pkt->set(lsr);
 177             break;
 178         case 0x6: // Modem Status Register (MSR)
 179             pkt->set((uint8_t)0);
 180             break;
 181         case 0x7: // Scratch Register (SCR)
 182             pkt->set((uint8_t)0); // doesn't exist with at 8250.
 183             break;
 184         default:
 185             panic("Tried to access a UART port that doesn't exist\n");
 186             break;
 187     }
 188 /*    uint32_t d32 = *data;
 189     DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
 190 */
 191     pkt->result = Packet::Success;
 192     return pioDelay;
 193 }
 194
 195 Tick
 196 Uart8250::write(PacketPtr pkt)
 197 {
 198
 199     assert(pkt->result == Packet::Unknown);
 200     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 201     assert(pkt->getSize() == 1);
 202
 203     Addr daddr = pkt->getAddr() - pioAddr;
 204
 205     DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
 206
 207     switch (daddr) {
 208         case 0x0:
 209             if (!(LCR & 0x80)) { // write byte
 210                 cons->out(pkt->get<uint8_t>());
 211                 platform->clearConsoleInt();
 212                 status &= ~TX_INT;
 213                 if (UART_IER_THRI & IER)
 214                     txIntrEvent.scheduleIntr();
 215             } else { // dll divisor latch
 216                ;
 217             }
 218             break;
 219         case 0x1:
 220             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 221                 IER = pkt->get<uint8_t>();
 222                 if (UART_IER_THRI & IER)
 223                 {
 224                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
 225                     txIntrEvent.scheduleIntr();
 226                 }
 227                 else
 228                 {
 229                     DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
 230                     if (txIntrEvent.scheduled())
 231                         txIntrEvent.deschedule();
 232                     if (status & TX_INT)
 233                         platform->clearConsoleInt();
 234                     status &= ~TX_INT;
 235                 }
 236
 237                 if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
 238                     DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
 239                     rxIntrEvent.scheduleIntr();
 240                 } else {
 241                     DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
 242                     if (rxIntrEvent.scheduled())
 243                         rxIntrEvent.deschedule();
 244                     if (status & RX_INT)
 245                         platform->clearConsoleInt();
 246                     status &= ~RX_INT;
 247                 }
 248              } else { // DLM divisor latch MSB
 249                 ;
 250             }
 251             break;
 252         case 0x2: // FIFO Control Register (FCR)
 253             break;
 254         case 0x3: // Line Control Register (LCR)
 255             LCR = pkt->get<uint8_t>();
 256             break;
 257         case 0x4: // Modem Control Register (MCR)
 258             if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
 259                     MCR = 0x9A;
 260             break;
 261         case 0x7: // Scratch Register (SCR)
 262             // We are emulating a 8250 so we don't have a scratch reg
 263             break;
 264         default:
 265             panic("Tried to access a UART port that doesn't exist\n");
 266             break;
 267     }
 268     pkt->result = Packet::Success;
 269     return pioDelay;
 270 }
 271
 272 void
 273 Uart8250::dataAvailable()
 274 {
 275     // if the kernel wants an interrupt when we have data
 276     if (IER & UART_IER_RDI)
 277     {
 278         platform->postConsoleInt();
 279         status |= RX_INT;
 280     }
 281
 282 }
 283
 284 void
 285 Uart8250::addressRanges(AddrRangeList &range_list)
 286 {
 287     assert(pioSize != 0);
 288     range_list.clear();
 289     range_list.push_back(RangeSize(pioAddr, pioSize));
 290 }
 291
 292
 293
 294 void
 295 Uart8250::serialize(ostream &os)
 296 {
 297     SERIALIZE_SCALAR(status);
 298     SERIALIZE_SCALAR(IER);
 299     SERIALIZE_SCALAR(DLAB);
 300     SERIALIZE_SCALAR(LCR);
 301     SERIALIZE_SCALAR(MCR);
 302     Tick rxintrwhen;
 303     if (rxIntrEvent.scheduled())
 304         rxintrwhen = rxIntrEvent.when();
 305     else
 306         rxintrwhen = 0;
 307     Tick txintrwhen;
 308     if (txIntrEvent.scheduled())
 309         txintrwhen = txIntrEvent.when();
 310     else
 311         txintrwhen = 0;
 312      SERIALIZE_SCALAR(rxintrwhen);
 313      SERIALIZE_SCALAR(txintrwhen);
 314 }
 315
 316 void
 317 Uart8250::unserialize(Checkpoint *cp, const std::string &section)
 318 {
 319     UNSERIALIZE_SCALAR(status);
 320     UNSERIALIZE_SCALAR(IER);
 321     UNSERIALIZE_SCALAR(DLAB);
 322     UNSERIALIZE_SCALAR(LCR);
 323     UNSERIALIZE_SCALAR(MCR);
 324     Tick rxintrwhen;
 325     Tick txintrwhen;
 326     UNSERIALIZE_SCALAR(rxintrwhen);
 327     UNSERIALIZE_SCALAR(txintrwhen);
 328     if (rxintrwhen != 0)
 329         rxIntrEvent.schedule(rxintrwhen);
 330     if (txintrwhen != 0)
 331         txIntrEvent.schedule(txintrwhen);
 332 }
 333
 334 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 335
 336     Param<Addr> pio_addr;
 337     Param<Tick> pio_latency;
 338     SimObjectParam<Platform *> platform;
 339     SimObjectParam<SimConsole *> sim_console;
 340     SimObjectParam<System *> system;
 341
 342 END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 343
 344 BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
 345
 346     INIT_PARAM(pio_addr, "Device Address"),
 347     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
 348     INIT_PARAM(platform, "platform"),
 349     INIT_PARAM(sim_console, "The Simulator Console"),
 350     INIT_PARAM(system, "system object")
 351
 352 END_INIT_SIM_OBJECT_PARAMS(Uart8250)
 353
 354 CREATE_SIM_OBJECT(Uart8250)
 355 {
 356     Uart8250::Params *p = new Uart8250::Params;
 357     p->name = getInstanceName();
 358     p->pio_addr = pio_addr;
 359     p->pio_delay = pio_latency;
 360     p->platform = platform;
 361     p->cons = sim_console;
 362     p->system = system;
 363     return new Uart8250(p);
 364 }
 365
 366 REGISTER_SIM_OBJECT("Uart8250", Uart8250)
 367