src/dev/uart8250.cc

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /** @file
  32  * Implements a 8250 UART
  33  */
  34
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/str.hh"        // for to_number
  40 #include "base/trace.hh"
  41 #include "config/the_isa.hh"
  42 #include "dev/platform.hh"
  43 #include "dev/terminal.hh"
  44 #include "dev/uart8250.hh"
  45 #include "mem/packet.hh"
  46 #include "mem/packet_access.hh"
  47
  48 using namespace std;
  49 using namespace TheISA;
  50
  51 Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
  52     : uart(u)
  53 {
  54     DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
  55     intrBit = bit;
  56 }
  57
  58 const char *
  59 Uart8250::IntrEvent::description() const
  60 {
  61     return "uart interrupt delay";
  62 }
  63
  64 void
  65 Uart8250::IntrEvent::process()
  66 {
  67     if (intrBit & uart->IER) {
  68        DPRINTF(Uart, "UART InterEvent, interrupting\n");
  69        uart->platform->postConsoleInt();
  70        uart->status |= intrBit;
  71        uart->lastTxInt = curTick;
  72     }
  73     else
  74        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
  75
  76 }
  77
  78 /* The linux serial driver (8250.c about line 1182) loops reading from
  79  * the device until the device reports it has no more data to
  80  * read. After a maximum of 255 iterations the code prints "serial8250
  81  * too much work for irq X," and breaks out of the loop. Since the
  82  * simulated system is so much slower than the actual system, if a
  83  * user is typing on the keyboard it is very easy for them to provide
  84  * input at a fast enough rate to not allow the loop to exit and thus
  85  * the error to be printed. This magic number provides a delay between
  86  * the time the UART receives a character to send to the simulated
  87  * system and the time it actually notifies the system it has a
  88  * character to send to alleviate this problem. --Ali
  89  */
  90 void
  91 Uart8250::IntrEvent::scheduleIntr()
  92 {
  93     static const Tick interval = 225 * SimClock::Int::ns;
  94     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
  95             curTick + interval);
  96     if (!scheduled())
  97         uart->schedule(this, curTick + interval);
  98     else
  99         uart->reschedule(this, curTick + interval);
 100 }
 101
 102
 103 Uart8250::Uart8250(const Params *p)
 104     : Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
 105       txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 106 {
 107     pioSize = 8;
 108 }
 109
 110 Tick
 111 Uart8250::read(PacketPtr pkt)
 112 {
 113     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 114     assert(pkt->getSize() == 1);
 115
 116     Addr daddr = pkt->getAddr() - pioAddr;
 117     pkt->allocate();
 118
 119     DPRINTF(Uart, " read register %#x\n", daddr);
 120
 121     switch (daddr) {
 122         case 0x0:
 123             if (!(LCR & 0x80)) { // read byte
 124                 if (term->dataAvailable())
 125                     pkt->set(term->in());
 126                 else {
 127                     pkt->set((uint8_t)0);
 128                     // A limited amount of these are ok.
 129                     DPRINTF(Uart, "empty read of RX register\n");
 130                 }
 131                 status &= ~RX_INT;
 132                 platform->clearConsoleInt();
 133
 134                 if (term->dataAvailable() && (IER & UART_IER_RDI))
 135                     rxIntrEvent.scheduleIntr();
 136             } else { // dll divisor latch
 137                ;
 138             }
 139             break;
 140         case 0x1:
 141             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 142                 pkt->set(IER);
 143             } else { // DLM divisor latch MSB
 144                 ;
 145             }
 146             break;
 147         case 0x2: // Intr Identification Register (IIR)
 148             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 149
 150             if (status & RX_INT) /* Rx data interrupt has a higher priority */
 151                 pkt->set(IIR_RXID);
 152             else if (status & TX_INT) {
 153                 pkt->set(IIR_TXID);
 154                 //Tx interrupts are cleared on IIR reads
 155                 status &= ~TX_INT;
 156             } else
 157                 pkt->set(IIR_NOPEND);
 158
 159             break;
 160         case 0x3: // Line Control Register (LCR)
 161             pkt->set(LCR);
 162             break;
 163         case 0x4: // Modem Control Register (MCR)
 164             pkt->set(MCR);
 165             break;
 166         case 0x5: // Line Status Register (LSR)
 167             uint8_t lsr;
 168             lsr = 0;
 169             // check if there are any bytes to be read
 170             if (term->dataAvailable())
 171                 lsr = UART_LSR_DR;
 172             lsr |= UART_LSR_TEMT | UART_LSR_THRE;
 173             pkt->set(lsr);
 174             break;
 175         case 0x6: // Modem Status Register (MSR)
 176             pkt->set((uint8_t)0);
 177             break;
 178         case 0x7: // Scratch Register (SCR)
 179             pkt->set((uint8_t)0); // doesn't exist with at 8250.
 180             break;
 181         default:
 182             panic("Tried to access a UART port that doesn't exist\n");
 183             break;
 184     }
 185 /*    uint32_t d32 = *data;
 186     DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
 187 */
 188     pkt->makeAtomicResponse();
 189     return pioDelay;
 190 }
 191
 192 Tick
 193 Uart8250::write(PacketPtr pkt)
 194 {
 195
 196     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 197     assert(pkt->getSize() == 1);
 198
 199     Addr daddr = pkt->getAddr() - pioAddr;
 200
 201     DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
 202
 203     switch (daddr) {
 204         case 0x0:
 205             if (!(LCR & 0x80)) { // write byte
 206                 term->out(pkt->get<uint8_t>());
 207                 platform->clearConsoleInt();
 208                 status &= ~TX_INT;
 209                 if (UART_IER_THRI & IER)
 210                     txIntrEvent.scheduleIntr();
 211             } else { // dll divisor latch
 212                ;
 213             }
 214             break;
 215         case 0x1:
 216             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 217                 IER = pkt->get<uint8_t>();
 218                 if (UART_IER_THRI & IER)
 219                 {
 220                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
 221                     if (curTick - lastTxInt > 225 * SimClock::Int::ns) {
 222                         DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
 223                                 curTick, lastTxInt);
 224                         txIntrEvent.process();
 225                     } else {
 226                         DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
 227                                 curTick, lastTxInt);
 228                         txIntrEvent.scheduleIntr();
 229                     }
 230                 }
 231                 else
 232                 {
 233                     DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
 234                     if (txIntrEvent.scheduled())
 235                         deschedule(txIntrEvent);
 236                     if (status & TX_INT)
 237                         platform->clearConsoleInt();
 238                     status &= ~TX_INT;
 239                 }
 240
 241                 if ((UART_IER_RDI & IER) && term->dataAvailable()) {
 242                     DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
 243                     rxIntrEvent.scheduleIntr();
 244                 } else {
 245                     DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
 246                     if (rxIntrEvent.scheduled())
 247                         deschedule(rxIntrEvent);
 248                     if (status & RX_INT)
 249                         platform->clearConsoleInt();
 250                     status &= ~RX_INT;
 251                 }
 252              } else { // DLM divisor latch MSB
 253                 ;
 254             }
 255             break;
 256         case 0x2: // FIFO Control Register (FCR)
 257             break;
 258         case 0x3: // Line Control Register (LCR)
 259             LCR = pkt->get<uint8_t>();
 260             break;
 261         case 0x4: // Modem Control Register (MCR)
 262             if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
 263                     MCR = 0x9A;
 264             break;
 265         case 0x7: // Scratch Register (SCR)
 266             // We are emulating a 8250 so we don't have a scratch reg
 267             break;
 268         default:
 269             panic("Tried to access a UART port that doesn't exist\n");
 270             break;
 271     }
 272     pkt->makeAtomicResponse();
 273     return pioDelay;
 274 }
 275
 276 void
 277 Uart8250::dataAvailable()
 278 {
 279     // if the kernel wants an interrupt when we have data
 280     if (IER & UART_IER_RDI)
 281     {
 282         platform->postConsoleInt();
 283         status |= RX_INT;
 284     }
 285
 286 }
 287
 288 void
 289 Uart8250::addressRanges(AddrRangeList &range_list)
 290 {
 291     assert(pioSize != 0);
 292     range_list.clear();
 293     range_list.push_back(RangeSize(pioAddr, pioSize));
 294 }
 295
 296
 297
 298 void
 299 Uart8250::serialize(ostream &os)
 300 {
 301     SERIALIZE_SCALAR(status);
 302     SERIALIZE_SCALAR(IER);
 303     SERIALIZE_SCALAR(DLAB);
 304     SERIALIZE_SCALAR(LCR);
 305     SERIALIZE_SCALAR(MCR);
 306     Tick rxintrwhen;
 307     if (rxIntrEvent.scheduled())
 308         rxintrwhen = rxIntrEvent.when();
 309     else
 310         rxintrwhen = 0;
 311     Tick txintrwhen;
 312     if (txIntrEvent.scheduled())
 313         txintrwhen = txIntrEvent.when();
 314     else
 315         txintrwhen = 0;
 316      SERIALIZE_SCALAR(rxintrwhen);
 317      SERIALIZE_SCALAR(txintrwhen);
 318 }
 319
 320 void
 321 Uart8250::unserialize(Checkpoint *cp, const std::string &section)
 322 {
 323     UNSERIALIZE_SCALAR(status);
 324     UNSERIALIZE_SCALAR(IER);
 325     UNSERIALIZE_SCALAR(DLAB);
 326     UNSERIALIZE_SCALAR(LCR);
 327     UNSERIALIZE_SCALAR(MCR);
 328     Tick rxintrwhen;
 329     Tick txintrwhen;
 330     UNSERIALIZE_SCALAR(rxintrwhen);
 331     UNSERIALIZE_SCALAR(txintrwhen);
 332     if (rxintrwhen != 0)
 333         schedule(rxIntrEvent, rxintrwhen);
 334     if (txintrwhen != 0)
 335         schedule(txIntrEvent, txintrwhen);
 336 }
 337
 338 Uart8250 *
 339 Uart8250Params::create()
 340 {
 341     return new Uart8250(this);
 342 }