src/dev/x86/PC.py

   1 # Copyright (c) 2008 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Gabe Black
  28
  29 from m5.params import *
  30 from m5.proxy import *
  31
  32 from Device import IsaFake
  33 from Pci import PciConfigAll
  34 from Platform import Platform
  35 from SouthBridge import SouthBridge
  36 from Terminal import Terminal
  37 from Uart import Uart8250
  38
  39 def x86IOAddress(port):
  40     IO_address_space_base = 0x8000000000000000
  41     return IO_address_space_base + port;
  42
  43 class PC(Platform):
  44     type = 'PC'
  45     system = Param.System(Parent.any, "system")
  46
  47     pciconfig = PciConfigAll()
  48
  49     south_bridge = SouthBridge()
  50
  51     # "Non-existant" port used for timing purposes by the linux kernel
  52     i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
  53
  54     # Ports behind the pci config and data regsiters. These don't do anything,
  55     # but the linux kernel fiddles with them anway.
  56     behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
  57
  58     # Serial port and terminal
  59     terminal = Terminal()
  60     com_1 = Uart8250()
  61     com_1.pio_addr = x86IOAddress(0x3f8)
  62     com_1.terminal = terminal
  63
  64     def attachIO(self, bus):
  65         self.south_bridge.pio = bus.port
  66         self.i_dont_exist.pio = bus.port
  67         self.behind_pci.pio = bus.port
  68         self.com_1.pio = bus.port
  69         self.pciconfig.pio = bus.default
  70         bus.responder_set = True
  71         bus.responder = self.pciconfig