1 # Copyright (c) 2008 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 from m5
.params
import *
30 from m5
.proxy
import *
32 from I8042
import I8042
33 from I82094AA
import I82094AA
34 from I8237
import I8237
35 from I8254
import I8254
36 from I8259
import I8259
37 from Ide
import IdeController
38 from PcSpeaker
import PcSpeaker
39 from X86IntPin
import X86IntLine
40 from m5
.SimObject
import SimObject
42 def x86IOAddress(port
):
43 IO_address_space_base
= 0x8000000000000000
44 return IO_address_space_base
+ port
;
46 class SouthBridge(SimObject
):
48 cxx_header
= "dev/x86/south_bridge.hh"
49 platform
= Param
.Platform(Parent
.any
, "Platform this device is part of")
51 _pic1
= I8259(pio_addr
=x86IOAddress(0x20), mode
='I8259Master')
52 _pic2
= I8259(pio_addr
=x86IOAddress(0xA0), mode
='I8259Slave')
53 _cmos
= Cmos(pio_addr
=x86IOAddress(0x70))
54 _dma1
= I8237(pio_addr
=x86IOAddress(0x0))
55 _keyboard
= I8042(data_port
=x86IOAddress(0x60), \
56 command_port
=x86IOAddress(0x64))
57 _pit
= I8254(pio_addr
=x86IOAddress(0x40))
58 _speaker
= PcSpeaker(pio_addr
=x86IOAddress(0x61))
59 _io_apic
= I82094AA(pio_addr
=0xFEC00000)
61 pic1
= Param
.I8259(_pic1
, "Master PIC")
62 pic2
= Param
.I8259(_pic2
, "Slave PIC")
63 cmos
= Param
.Cmos(_cmos
, "CMOS memory and real time clock device")
64 dma1
= Param
.I8237(_dma1
, "The first dma controller")
65 keyboard
= Param
.I8042(_keyboard
, "The keyboard controller")
66 pit
= Param
.I8254(_pit
, "Programmable interval timer")
67 speaker
= Param
.PcSpeaker(_speaker
, "PC speaker")
68 io_apic
= Param
.I82094AA(_io_apic
, "I/O APIC")
71 ide
= IdeController(disks
=[], pci_func
=0, pci_dev
=4, pci_bus
=0)
73 ide
.BAR0LegacyIO
= True
76 ide
.BAR1LegacyIO
= True
78 ide
.BAR2LegacyIO
= True
81 ide
.BAR3LegacyIO
= True
85 ide
.InterruptLine
= 14
87 ide
.LegacyIOBase
= x86IOAddress(0)
89 def attachIO(self
, bus
, dma_ports
):
90 # Route interupt signals
92 [X86IntLine(source
=self
.pic1
.output
, sink
=self
.io_apic
.pin(0)),
93 X86IntLine(source
=self
.pic2
.output
, sink
=self
.pic1
.pin(2)),
94 X86IntLine(source
=self
.cmos
.int_pin
, sink
=self
.pic2
.pin(0)),
95 X86IntLine(source
=self
.pit
.int_pin
, sink
=self
.pic1
.pin(0)),
96 X86IntLine(source
=self
.pit
.int_pin
, sink
=self
.io_apic
.pin(2)),
97 X86IntLine(source
=self
.keyboard
.keyboard_int_pin
,
98 sink
=self
.io_apic
.pin(1)),
99 X86IntLine(source
=self
.keyboard
.mouse_int_pin
,
100 sink
=self
.io_apic
.pin(12))]
101 # Tell the devices about each other
102 self
.pic1
.slave
= self
.pic2
103 self
.speaker
.i8254
= self
.pit
104 self
.io_apic
.external_int_pic
= self
.pic1
106 self
.cmos
.pio
= bus
.master
107 self
.dma1
.pio
= bus
.master
108 self
.ide
.pio
= bus
.master
109 if dma_ports
.count(self
.ide
.dma
) == 0:
110 self
.ide
.dma
= bus
.slave
111 self
.keyboard
.pio
= bus
.master
112 self
.pic1
.pio
= bus
.master
113 self
.pic2
.pio
= bus
.master
114 self
.pit
.pio
= bus
.master
115 self
.speaker
.pio
= bus
.master
116 self
.io_apic
.pio
= bus
.master
117 self
.io_apic
.int_master
= bus
.slave