src/dev/x86/SouthBridge.py

   1 # Copyright (c) 2008 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Gabe Black
  28
  29 from m5.params import *
  30 from m5.proxy import *
  31 from m5.objects.Cmos import Cmos
  32 from m5.objects.I8042 import I8042
  33 from m5.objects.I82094AA import I82094AA
  34 from m5.objects.I8237 import I8237
  35 from m5.objects.I8254 import I8254
  36 from m5.objects.I8259 import I8259
  37 from m5.objects.Ide import IdeController
  38 from m5.objects.PcSpeaker import PcSpeaker
  39 from m5.SimObject import SimObject
  40
  41 def x86IOAddress(port):
  42     IO_address_space_base = 0x8000000000000000
  43     return IO_address_space_base + port;
  44
  45 class SouthBridge(SimObject):
  46     type = 'SouthBridge'
  47     cxx_header = "dev/x86/south_bridge.hh"
  48     platform = Param.Platform(Parent.any, "Platform this device is part of")
  49
  50     _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
  51     _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
  52     _cmos = Cmos(pio_addr=x86IOAddress(0x70))
  53     _dma1 = I8237(pio_addr=x86IOAddress(0x0))
  54     _keyboard = I8042(data_port=x86IOAddress(0x60), \
  55             command_port=x86IOAddress(0x64))
  56     _pit = I8254(pio_addr=x86IOAddress(0x40))
  57     _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
  58     _io_apic = I82094AA(pio_addr=0xFEC00000)
  59
  60     pic1 = Param.I8259(_pic1, "Master PIC")
  61     pic2 = Param.I8259(_pic2, "Slave PIC")
  62     cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
  63     dma1 = Param.I8237(_dma1, "The first dma controller")
  64     keyboard = Param.I8042(_keyboard, "The keyboard controller")
  65     pit = Param.I8254(_pit, "Programmable interval timer")
  66     speaker = Param.PcSpeaker(_speaker, "PC speaker")
  67     io_apic = Param.I82094AA(_io_apic, "I/O APIC")
  68
  69     # IDE controller
  70     ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
  71     ide.BAR0 = 0x1f0
  72     ide.BAR0LegacyIO = True
  73     ide.BAR1 = 0x3f4
  74     ide.BAR1Size = '3B'
  75     ide.BAR1LegacyIO = True
  76     ide.BAR2 = 0x170
  77     ide.BAR2LegacyIO = True
  78     ide.BAR3 = 0x374
  79     ide.BAR3Size = '3B'
  80     ide.BAR3LegacyIO = True
  81     ide.BAR4 = 1
  82     ide.Command = 0
  83     ide.ProgIF = 0x80
  84     ide.InterruptLine = 14
  85     ide.InterruptPin = 1
  86     ide.LegacyIOBase = x86IOAddress(0)
  87
  88     def attachIO(self, bus, dma_ports):
  89         # Route interrupt signals
  90         self.pic1.output = self.io_apic.inputs[0]
  91         self.pic2.output = self.pic1.inputs[2]
  92         self.cmos.int_pin = self.pic2.inputs[0]
  93         self.pit.int_pin = self.pic1.inputs[0]
  94         self.pit.int_pin = self.io_apic.inputs[2]
  95         self.keyboard.keyboard_int_pin = self.io_apic.inputs[1]
  96         self.keyboard.mouse_int_pin = self.io_apic.inputs[12]
  97         # Tell the devices about each other
  98         self.pic1.slave = self.pic2
  99         self.speaker.i8254 = self.pit
 100         self.io_apic.external_int_pic = self.pic1
 101         # Connect to the bus
 102         self.cmos.pio = bus.master
 103         self.dma1.pio = bus.master
 104         self.ide.pio = bus.master
 105         if dma_ports.count(self.ide.dma) == 0:
 106                 self.ide.dma = bus.slave
 107         self.keyboard.pio = bus.master
 108         self.pic1.pio = bus.master
 109         self.pic2.pio = bus.master
 110         self.pit.pio = bus.master
 111         self.speaker.pio = bus.master
 112         self.io_apic.pio = bus.master
 113         self.io_apic.int_master = bus.slave