src/dev/x86/i82094aa.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #include "dev/x86/i82094aa.hh"
  32
  33 #include <list>
  34
  35 #include "arch/x86/interrupts.hh"
  36 #include "arch/x86/intmessage.hh"
  37 #include "cpu/base.hh"
  38 #include "debug/I82094AA.hh"
  39 #include "dev/x86/i8259.hh"
  40 #include "mem/packet.hh"
  41 #include "mem/packet_access.hh"
  42 #include "sim/system.hh"
  43
  44 X86ISA::I82094AA::I82094AA(Params *p)
  45     : BasicPioDevice(p, 20), extIntPic(p->external_int_pic),
  46       lowestPriorityOffset(0),
  47       intMasterPort(name() + ".int_master", this, this, p->int_latency)
  48 {
  49     // This assumes there's only one I/O APIC in the system and since the apic
  50     // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
  51     // be less than 0xff
  52
  53     assert(p->apic_id < 0xff);
  54     initialApicId = id = p->apic_id;
  55     arbId = id;
  56     regSel = 0;
  57     RedirTableEntry entry = 0;
  58     entry.mask = 1;
  59     for (int i = 0; i < TableSize; i++) {
  60         redirTable[i] = entry;
  61         pinStates[i] = false;
  62     }
  63
  64     for (int i = 0; i < p->port_inputs_connection_count; i++)
  65         inputs.push_back(new IntSinkPin<I82094AA>(
  66                     csprintf("%s.inputs[%d]", name(), i), i, this));
  67 }
  68
  69 void
  70 X86ISA::I82094AA::init()
  71 {
  72     // The io apic must register its address range with its pio port via
  73     // the piodevice init() function.
  74     BasicPioDevice::init();
  75
  76     // If the master port isn't connected, we can't send interrupts anywhere.
  77     panic_if(!intMasterPort.isConnected(),
  78             "Int port not connected to anything!");
  79 }
  80
  81 Port &
  82 X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
  83 {
  84     if (if_name == "int_master")
  85         return intMasterPort;
  86     if (if_name == "inputs")
  87         return *inputs.at(idx);
  88     else
  89         return BasicPioDevice::getPort(if_name, idx);
  90 }
  91
  92 Tick
  93 X86ISA::I82094AA::read(PacketPtr pkt)
  94 {
  95     assert(pkt->getSize() == 4);
  96     Addr offset = pkt->getAddr() - pioAddr;
  97     switch(offset) {
  98       case 0:
  99         pkt->setLE<uint32_t>(regSel);
 100         break;
 101       case 16:
 102         pkt->setLE<uint32_t>(readReg(regSel));
 103         break;
 104       default:
 105         panic("Illegal read from I/O APIC.\n");
 106     }
 107     pkt->makeAtomicResponse();
 108     return pioDelay;
 109 }
 110
 111 Tick
 112 X86ISA::I82094AA::write(PacketPtr pkt)
 113 {
 114     assert(pkt->getSize() == 4);
 115     Addr offset = pkt->getAddr() - pioAddr;
 116     switch(offset) {
 117       case 0:
 118         regSel = pkt->getLE<uint32_t>();
 119         break;
 120       case 16:
 121         writeReg(regSel, pkt->getLE<uint32_t>());
 122         break;
 123       default:
 124         panic("Illegal write to I/O APIC.\n");
 125     }
 126     pkt->makeAtomicResponse();
 127     return pioDelay;
 128 }
 129
 130 void
 131 X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
 132 {
 133     if (offset == 0x0) {
 134         id = bits(value, 31, 24);
 135     } else if (offset == 0x1) {
 136         // The IOAPICVER register is read only.
 137     } else if (offset == 0x2) {
 138         arbId = bits(value, 31, 24);
 139     } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
 140         int index = (offset - 0x10) / 2;
 141         if (offset % 2) {
 142             redirTable[index].topDW = value;
 143             redirTable[index].topReserved = 0;
 144         } else {
 145             redirTable[index].bottomDW = value;
 146             redirTable[index].bottomReserved = 0;
 147         }
 148     } else {
 149         warn("Access to undefined I/O APIC register %#x.\n", offset);
 150     }
 151     DPRINTF(I82094AA,
 152             "Wrote %#x to I/O APIC register %#x .\n", value, offset);
 153 }
 154
 155 uint32_t
 156 X86ISA::I82094AA::readReg(uint8_t offset)
 157 {
 158     uint32_t result = 0;
 159     if (offset == 0x0) {
 160         result = id << 24;
 161     } else if (offset == 0x1) {
 162         result = ((TableSize - 1) << 16) | APICVersion;
 163     } else if (offset == 0x2) {
 164         result = arbId << 24;
 165     } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
 166         int index = (offset - 0x10) / 2;
 167         if (offset % 2) {
 168             result = redirTable[index].topDW;
 169         } else {
 170             result = redirTable[index].bottomDW;
 171         }
 172     } else {
 173         warn("Access to undefined I/O APIC register %#x.\n", offset);
 174     }
 175     DPRINTF(I82094AA,
 176             "Read %#x from I/O APIC register %#x.\n", result, offset);
 177     return result;
 178 }
 179
 180 void
 181 X86ISA::I82094AA::signalInterrupt(int line)
 182 {
 183     DPRINTF(I82094AA, "Received interrupt %d.\n", line);
 184     assert(line < TableSize);
 185     RedirTableEntry entry = redirTable[line];
 186     if (entry.mask) {
 187         DPRINTF(I82094AA, "Entry was masked.\n");
 188         return;
 189     } else {
 190         TriggerIntMessage message = 0;
 191         message.destination = entry.dest;
 192         if (entry.deliveryMode == DeliveryMode::ExtInt) {
 193             assert(extIntPic);
 194             message.vector = extIntPic->getVector();
 195         } else {
 196             message.vector = entry.vector;
 197         }
 198         message.deliveryMode = entry.deliveryMode;
 199         message.destMode = entry.destMode;
 200         message.level = entry.polarity;
 201         message.trigger = entry.trigger;
 202         std::list<int> apics;
 203         int numContexts = sys->numContexts();
 204         if (message.destMode == 0) {
 205             if (message.deliveryMode == DeliveryMode::LowestPriority) {
 206                 panic("Lowest priority delivery mode from the "
 207                         "IO APIC aren't supported in physical "
 208                         "destination mode.\n");
 209             }
 210             if (message.destination == 0xFF) {
 211                 for (int i = 0; i < numContexts; i++) {
 212                     apics.push_back(i);
 213                 }
 214             } else {
 215                 apics.push_back(message.destination);
 216             }
 217         } else {
 218             for (int i = 0; i < numContexts; i++) {
 219                 BaseInterrupts *base_int = sys->getThreadContext(i)->
 220                     getCpuPtr()->getInterruptController(0);
 221                 auto *localApic = dynamic_cast<Interrupts *>(base_int);
 222                 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
 223                         message.destination) {
 224                     apics.push_back(localApic->getInitialApicId());
 225                 }
 226             }
 227             if (message.deliveryMode == DeliveryMode::LowestPriority &&
 228                     apics.size()) {
 229                 // The manual seems to suggest that the chipset just does
 230                 // something reasonable for these instead of actually using
 231                 // state from the local APIC. We'll just rotate an offset
 232                 // through the set of APICs selected above.
 233                 uint64_t modOffset = lowestPriorityOffset % apics.size();
 234                 lowestPriorityOffset++;
 235                 auto apicIt = apics.begin();
 236                 while (modOffset--) {
 237                     apicIt++;
 238                     assert(apicIt != apics.end());
 239                 }
 240                 int selected = *apicIt;
 241                 apics.clear();
 242                 apics.push_back(selected);
 243             }
 244         }
 245         for (auto id: apics) {
 246             PacketPtr pkt = buildIntTriggerPacket(id, message);
 247             intMasterPort.sendMessage(pkt, sys->isTimingMode());
 248         }
 249     }
 250 }
 251
 252 void
 253 X86ISA::I82094AA::raiseInterruptPin(int number)
 254 {
 255     assert(number < TableSize);
 256     if (!pinStates[number])
 257         signalInterrupt(number);
 258     pinStates[number] = true;
 259 }
 260
 261 void
 262 X86ISA::I82094AA::lowerInterruptPin(int number)
 263 {
 264     assert(number < TableSize);
 265     pinStates[number] = false;
 266 }
 267
 268 void
 269 X86ISA::I82094AA::serialize(CheckpointOut &cp) const
 270 {
 271     uint64_t* redirTableArray = (uint64_t*)redirTable;
 272     SERIALIZE_SCALAR(regSel);
 273     SERIALIZE_SCALAR(initialApicId);
 274     SERIALIZE_SCALAR(id);
 275     SERIALIZE_SCALAR(arbId);
 276     SERIALIZE_SCALAR(lowestPriorityOffset);
 277     SERIALIZE_ARRAY(redirTableArray, TableSize);
 278     SERIALIZE_ARRAY(pinStates, TableSize);
 279 }
 280
 281 void
 282 X86ISA::I82094AA::unserialize(CheckpointIn &cp)
 283 {
 284     uint64_t redirTableArray[TableSize];
 285     UNSERIALIZE_SCALAR(regSel);
 286     UNSERIALIZE_SCALAR(initialApicId);
 287     UNSERIALIZE_SCALAR(id);
 288     UNSERIALIZE_SCALAR(arbId);
 289     UNSERIALIZE_SCALAR(lowestPriorityOffset);
 290     UNSERIALIZE_ARRAY(redirTableArray, TableSize);
 291     UNSERIALIZE_ARRAY(pinStates, TableSize);
 292     for (int i = 0; i < TableSize; i++) {
 293         redirTable[i] = (RedirTableEntry)redirTableArray[i];
 294     }
 295 }
 296
 297 X86ISA::I82094AA *
 298 I82094AAParams::create()
 299 {
 300     return new X86ISA::I82094AA(this);
 301 }