src/dev/x86/i82094aa.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "dev/x86/i82094aa.hh"
  30
  31 #include <list>
  32
  33 #include "arch/x86/interrupts.hh"
  34 #include "arch/x86/intmessage.hh"
  35 #include "cpu/base.hh"
  36 #include "debug/I82094AA.hh"
  37 #include "dev/x86/i8259.hh"
  38 #include "mem/packet.hh"
  39 #include "mem/packet_access.hh"
  40 #include "sim/system.hh"
  41
  42 X86ISA::I82094AA::I82094AA(Params *p)
  43     : BasicPioDevice(p, 20), extIntPic(p->external_int_pic),
  44       lowestPriorityOffset(0),
  45       intRequestPort(name() + ".int_request", this, this, p->int_latency)
  46 {
  47     // This assumes there's only one I/O APIC in the system and since the apic
  48     // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
  49     // be less than 0xff
  50
  51     assert(p->apic_id < 0xff);
  52     initialApicId = id = p->apic_id;
  53     arbId = id;
  54     regSel = 0;
  55     RedirTableEntry entry = 0;
  56     entry.mask = 1;
  57     for (int i = 0; i < TableSize; i++) {
  58         redirTable[i] = entry;
  59         pinStates[i] = false;
  60     }
  61
  62     for (int i = 0; i < p->port_inputs_connection_count; i++)
  63         inputs.push_back(new IntSinkPin<I82094AA>(
  64                     csprintf("%s.inputs[%d]", name(), i), i, this));
  65 }
  66
  67 void
  68 X86ISA::I82094AA::init()
  69 {
  70     // The io apic must register its address range with its pio port via
  71     // the piodevice init() function.
  72     BasicPioDevice::init();
  73
  74     // If the request port isn't connected, we can't send interrupts anywhere.
  75     panic_if(!intRequestPort.isConnected(),
  76             "Int port not connected to anything!");
  77 }
  78
  79 Port &
  80 X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
  81 {
  82     if (if_name == "int_request")
  83         return intRequestPort;
  84     if (if_name == "inputs")
  85         return *inputs.at(idx);
  86     else
  87         return BasicPioDevice::getPort(if_name, idx);
  88 }
  89
  90 Tick
  91 X86ISA::I82094AA::read(PacketPtr pkt)
  92 {
  93     assert(pkt->getSize() == 4);
  94     Addr offset = pkt->getAddr() - pioAddr;
  95     switch(offset) {
  96       case 0:
  97         pkt->setLE<uint32_t>(regSel);
  98         break;
  99       case 16:
 100         pkt->setLE<uint32_t>(readReg(regSel));
 101         break;
 102       default:
 103         panic("Illegal read from I/O APIC.\n");
 104     }
 105     pkt->makeAtomicResponse();
 106     return pioDelay;
 107 }
 108
 109 Tick
 110 X86ISA::I82094AA::write(PacketPtr pkt)
 111 {
 112     assert(pkt->getSize() == 4);
 113     Addr offset = pkt->getAddr() - pioAddr;
 114     switch(offset) {
 115       case 0:
 116         regSel = pkt->getLE<uint32_t>();
 117         break;
 118       case 16:
 119         writeReg(regSel, pkt->getLE<uint32_t>());
 120         break;
 121       default:
 122         panic("Illegal write to I/O APIC.\n");
 123     }
 124     pkt->makeAtomicResponse();
 125     return pioDelay;
 126 }
 127
 128 void
 129 X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
 130 {
 131     if (offset == 0x0) {
 132         id = bits(value, 31, 24);
 133     } else if (offset == 0x1) {
 134         // The IOAPICVER register is read only.
 135     } else if (offset == 0x2) {
 136         arbId = bits(value, 31, 24);
 137     } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
 138         int index = (offset - 0x10) / 2;
 139         if (offset % 2) {
 140             redirTable[index].topDW = value;
 141             redirTable[index].topReserved = 0;
 142         } else {
 143             redirTable[index].bottomDW = value;
 144             redirTable[index].bottomReserved = 0;
 145         }
 146     } else {
 147         warn("Access to undefined I/O APIC register %#x.\n", offset);
 148     }
 149     DPRINTF(I82094AA,
 150             "Wrote %#x to I/O APIC register %#x .\n", value, offset);
 151 }
 152
 153 uint32_t
 154 X86ISA::I82094AA::readReg(uint8_t offset)
 155 {
 156     uint32_t result = 0;
 157     if (offset == 0x0) {
 158         result = id << 24;
 159     } else if (offset == 0x1) {
 160         result = ((TableSize - 1) << 16) | APICVersion;
 161     } else if (offset == 0x2) {
 162         result = arbId << 24;
 163     } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
 164         int index = (offset - 0x10) / 2;
 165         if (offset % 2) {
 166             result = redirTable[index].topDW;
 167         } else {
 168             result = redirTable[index].bottomDW;
 169         }
 170     } else {
 171         warn("Access to undefined I/O APIC register %#x.\n", offset);
 172     }
 173     DPRINTF(I82094AA,
 174             "Read %#x from I/O APIC register %#x.\n", result, offset);
 175     return result;
 176 }
 177
 178 void
 179 X86ISA::I82094AA::signalInterrupt(int line)
 180 {
 181     DPRINTF(I82094AA, "Received interrupt %d.\n", line);
 182     assert(line < TableSize);
 183     RedirTableEntry entry = redirTable[line];
 184     if (entry.mask) {
 185         DPRINTF(I82094AA, "Entry was masked.\n");
 186         return;
 187     } else {
 188         TriggerIntMessage message = 0;
 189         message.destination = entry.dest;
 190         if (entry.deliveryMode == DeliveryMode::ExtInt) {
 191             assert(extIntPic);
 192             message.vector = extIntPic->getVector();
 193         } else {
 194             message.vector = entry.vector;
 195         }
 196         message.deliveryMode = entry.deliveryMode;
 197         message.destMode = entry.destMode;
 198         message.level = entry.polarity;
 199         message.trigger = entry.trigger;
 200         std::list<int> apics;
 201         int numContexts = sys->threads.size();
 202         if (message.destMode == 0) {
 203             if (message.deliveryMode == DeliveryMode::LowestPriority) {
 204                 panic("Lowest priority delivery mode from the "
 205                         "IO APIC aren't supported in physical "
 206                         "destination mode.\n");
 207             }
 208             if (message.destination == 0xFF) {
 209                 for (int i = 0; i < numContexts; i++) {
 210                     apics.push_back(i);
 211                 }
 212             } else {
 213                 apics.push_back(message.destination);
 214             }
 215         } else {
 216             for (int i = 0; i < numContexts; i++) {
 217                 BaseInterrupts *base_int = sys->threads[i]->
 218                     getCpuPtr()->getInterruptController(0);
 219                 auto *localApic = dynamic_cast<Interrupts *>(base_int);
 220                 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
 221                         message.destination) {
 222                     apics.push_back(localApic->getInitialApicId());
 223                 }
 224             }
 225             if (message.deliveryMode == DeliveryMode::LowestPriority &&
 226                     apics.size()) {
 227                 // The manual seems to suggest that the chipset just does
 228                 // something reasonable for these instead of actually using
 229                 // state from the local APIC. We'll just rotate an offset
 230                 // through the set of APICs selected above.
 231                 uint64_t modOffset = lowestPriorityOffset % apics.size();
 232                 lowestPriorityOffset++;
 233                 auto apicIt = apics.begin();
 234                 while (modOffset--) {
 235                     apicIt++;
 236                     assert(apicIt != apics.end());
 237                 }
 238                 int selected = *apicIt;
 239                 apics.clear();
 240                 apics.push_back(selected);
 241             }
 242         }
 243         for (auto id: apics) {
 244             PacketPtr pkt = buildIntTriggerPacket(id, message);
 245             intRequestPort.sendMessage(pkt, sys->isTimingMode());
 246         }
 247     }
 248 }
 249
 250 void
 251 X86ISA::I82094AA::raiseInterruptPin(int number)
 252 {
 253     assert(number < TableSize);
 254     if (!pinStates[number])
 255         signalInterrupt(number);
 256     pinStates[number] = true;
 257 }
 258
 259 void
 260 X86ISA::I82094AA::lowerInterruptPin(int number)
 261 {
 262     assert(number < TableSize);
 263     pinStates[number] = false;
 264 }
 265
 266 void
 267 X86ISA::I82094AA::serialize(CheckpointOut &cp) const
 268 {
 269     uint64_t* redirTableArray = (uint64_t*)redirTable;
 270     SERIALIZE_SCALAR(regSel);
 271     SERIALIZE_SCALAR(initialApicId);
 272     SERIALIZE_SCALAR(id);
 273     SERIALIZE_SCALAR(arbId);
 274     SERIALIZE_SCALAR(lowestPriorityOffset);
 275     SERIALIZE_ARRAY(redirTableArray, TableSize);
 276     SERIALIZE_ARRAY(pinStates, TableSize);
 277 }
 278
 279 void
 280 X86ISA::I82094AA::unserialize(CheckpointIn &cp)
 281 {
 282     uint64_t redirTableArray[TableSize];
 283     UNSERIALIZE_SCALAR(regSel);
 284     UNSERIALIZE_SCALAR(initialApicId);
 285     UNSERIALIZE_SCALAR(id);
 286     UNSERIALIZE_SCALAR(arbId);
 287     UNSERIALIZE_SCALAR(lowestPriorityOffset);
 288     UNSERIALIZE_ARRAY(redirTableArray, TableSize);
 289     UNSERIALIZE_ARRAY(pinStates, TableSize);
 290     for (int i = 0; i < TableSize; i++) {
 291         redirTable[i] = (RedirTableEntry)redirTableArray[i];
 292     }
 293 }
 294
 295 X86ISA::I82094AA *
 296 I82094AAParams::create()
 297 {
 298     return new X86ISA::I82094AA(this);
 299 }