src/dev/x86/i82094aa.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #include "dev/x86/i82094aa.hh"
  32
  33 #include "arch/x86/interrupts.hh"
  34 #include "arch/x86/intmessage.hh"
  35 #include "cpu/base.hh"
  36 #include "debug/I82094AA.hh"
  37 #include "dev/x86/i8259.hh"
  38 #include "mem/packet.hh"
  39 #include "mem/packet_access.hh"
  40 #include "sim/system.hh"
  41
  42 X86ISA::I82094AA::I82094AA(Params *p)
  43     : BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
  44       extIntPic(p->external_int_pic), lowestPriorityOffset(0)
  45 {
  46     // This assumes there's only one I/O APIC in the system and since the apic
  47     // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
  48     // be less than 0xff
  49
  50     assert(p->apic_id < 0xff);
  51     initialApicId = id = p->apic_id;
  52     arbId = id;
  53     regSel = 0;
  54     RedirTableEntry entry = 0;
  55     entry.mask = 1;
  56     for (int i = 0; i < TableSize; i++) {
  57         redirTable[i] = entry;
  58         pinStates[i] = false;
  59     }
  60 }
  61
  62 void
  63 X86ISA::I82094AA::init()
  64 {
  65     // The io apic must register its address ranges on both its pio port
  66     // via the piodevice init() function and its int port that it inherited
  67     // from IntDevice.  Note IntDevice is not a SimObject itself.
  68
  69     BasicPioDevice::init();
  70     IntDevice::init();
  71 }
  72
  73 Port &
  74 X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
  75 {
  76     if (if_name == "int_master")
  77         return intMasterPort;
  78     return BasicPioDevice::getPort(if_name, idx);
  79 }
  80
  81 AddrRangeList
  82 X86ISA::I82094AA::getIntAddrRange() const
  83 {
  84     AddrRangeList ranges;
  85     ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
  86                              x86InterruptAddress(initialApicId, 0) +
  87                              PhysAddrAPICRangeSize));
  88     return ranges;
  89 }
  90
  91 Tick
  92 X86ISA::I82094AA::recvResponse(PacketPtr pkt)
  93 {
  94     // Packet instantiated calling sendMessage() in signalInterrupt()
  95     delete pkt;
  96     return 0;
  97 }
  98
  99 Tick
 100 X86ISA::I82094AA::read(PacketPtr pkt)
 101 {
 102     assert(pkt->getSize() == 4);
 103     Addr offset = pkt->getAddr() - pioAddr;
 104     switch(offset) {
 105       case 0:
 106         pkt->setLE<uint32_t>(regSel);
 107         break;
 108       case 16:
 109         pkt->setLE<uint32_t>(readReg(regSel));
 110         break;
 111       default:
 112         panic("Illegal read from I/O APIC.\n");
 113     }
 114     pkt->makeAtomicResponse();
 115     return pioDelay;
 116 }
 117
 118 Tick
 119 X86ISA::I82094AA::write(PacketPtr pkt)
 120 {
 121     assert(pkt->getSize() == 4);
 122     Addr offset = pkt->getAddr() - pioAddr;
 123     switch(offset) {
 124       case 0:
 125         regSel = pkt->getLE<uint32_t>();
 126         break;
 127       case 16:
 128         writeReg(regSel, pkt->getLE<uint32_t>());
 129         break;
 130       default:
 131         panic("Illegal write to I/O APIC.\n");
 132     }
 133     pkt->makeAtomicResponse();
 134     return pioDelay;
 135 }
 136
 137 void
 138 X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
 139 {
 140     if (offset == 0x0) {
 141         id = bits(value, 31, 24);
 142     } else if (offset == 0x1) {
 143         // The IOAPICVER register is read only.
 144     } else if (offset == 0x2) {
 145         arbId = bits(value, 31, 24);
 146     } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
 147         int index = (offset - 0x10) / 2;
 148         if (offset % 2) {
 149             redirTable[index].topDW = value;
 150             redirTable[index].topReserved = 0;
 151         } else {
 152             redirTable[index].bottomDW = value;
 153             redirTable[index].bottomReserved = 0;
 154         }
 155     } else {
 156         warn("Access to undefined I/O APIC register %#x.\n", offset);
 157     }
 158     DPRINTF(I82094AA,
 159             "Wrote %#x to I/O APIC register %#x .\n", value, offset);
 160 }
 161
 162 uint32_t
 163 X86ISA::I82094AA::readReg(uint8_t offset)
 164 {
 165     uint32_t result = 0;
 166     if (offset == 0x0) {
 167         result = id << 24;
 168     } else if (offset == 0x1) {
 169         result = ((TableSize - 1) << 16) | APICVersion;
 170     } else if (offset == 0x2) {
 171         result = arbId << 24;
 172     } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
 173         int index = (offset - 0x10) / 2;
 174         if (offset % 2) {
 175             result = redirTable[index].topDW;
 176         } else {
 177             result = redirTable[index].bottomDW;
 178         }
 179     } else {
 180         warn("Access to undefined I/O APIC register %#x.\n", offset);
 181     }
 182     DPRINTF(I82094AA,
 183             "Read %#x from I/O APIC register %#x.\n", result, offset);
 184     return result;
 185 }
 186
 187 void
 188 X86ISA::I82094AA::signalInterrupt(int line)
 189 {
 190     DPRINTF(I82094AA, "Received interrupt %d.\n", line);
 191     assert(line < TableSize);
 192     RedirTableEntry entry = redirTable[line];
 193     if (entry.mask) {
 194         DPRINTF(I82094AA, "Entry was masked.\n");
 195         return;
 196     } else {
 197         TriggerIntMessage message = 0;
 198         message.destination = entry.dest;
 199         if (entry.deliveryMode == DeliveryMode::ExtInt) {
 200             assert(extIntPic);
 201             message.vector = extIntPic->getVector();
 202         } else {
 203             message.vector = entry.vector;
 204         }
 205         message.deliveryMode = entry.deliveryMode;
 206         message.destMode = entry.destMode;
 207         message.level = entry.polarity;
 208         message.trigger = entry.trigger;
 209         ApicList apics;
 210         int numContexts = sys->numContexts();
 211         if (message.destMode == 0) {
 212             if (message.deliveryMode == DeliveryMode::LowestPriority) {
 213                 panic("Lowest priority delivery mode from the "
 214                         "IO APIC aren't supported in physical "
 215                         "destination mode.\n");
 216             }
 217             if (message.destination == 0xFF) {
 218                 for (int i = 0; i < numContexts; i++) {
 219                     apics.push_back(i);
 220                 }
 221             } else {
 222                 apics.push_back(message.destination);
 223             }
 224         } else {
 225             for (int i = 0; i < numContexts; i++) {
 226                 Interrupts *localApic = sys->getThreadContext(i)->
 227                     getCpuPtr()->getInterruptController(0);
 228                 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
 229                         message.destination) {
 230                     apics.push_back(localApic->getInitialApicId());
 231                 }
 232             }
 233             if (message.deliveryMode == DeliveryMode::LowestPriority &&
 234                     apics.size()) {
 235                 // The manual seems to suggest that the chipset just does
 236                 // something reasonable for these instead of actually using
 237                 // state from the local APIC. We'll just rotate an offset
 238                 // through the set of APICs selected above.
 239                 uint64_t modOffset = lowestPriorityOffset % apics.size();
 240                 lowestPriorityOffset++;
 241                 ApicList::iterator apicIt = apics.begin();
 242                 while (modOffset--) {
 243                     apicIt++;
 244                     assert(apicIt != apics.end());
 245                 }
 246                 int selected = *apicIt;
 247                 apics.clear();
 248                 apics.push_back(selected);
 249             }
 250         }
 251         intMasterPort.sendMessage(apics, message, sys->isTimingMode());
 252     }
 253 }
 254
 255 void
 256 X86ISA::I82094AA::raiseInterruptPin(int number)
 257 {
 258     assert(number < TableSize);
 259     if (!pinStates[number])
 260         signalInterrupt(number);
 261     pinStates[number] = true;
 262 }
 263
 264 void
 265 X86ISA::I82094AA::lowerInterruptPin(int number)
 266 {
 267     assert(number < TableSize);
 268     pinStates[number] = false;
 269 }
 270
 271 void
 272 X86ISA::I82094AA::serialize(CheckpointOut &cp) const
 273 {
 274     uint64_t* redirTableArray = (uint64_t*)redirTable;
 275     SERIALIZE_SCALAR(regSel);
 276     SERIALIZE_SCALAR(initialApicId);
 277     SERIALIZE_SCALAR(id);
 278     SERIALIZE_SCALAR(arbId);
 279     SERIALIZE_SCALAR(lowestPriorityOffset);
 280     SERIALIZE_ARRAY(redirTableArray, TableSize);
 281     SERIALIZE_ARRAY(pinStates, TableSize);
 282 }
 283
 284 void
 285 X86ISA::I82094AA::unserialize(CheckpointIn &cp)
 286 {
 287     uint64_t redirTableArray[TableSize];
 288     UNSERIALIZE_SCALAR(regSel);
 289     UNSERIALIZE_SCALAR(initialApicId);
 290     UNSERIALIZE_SCALAR(id);
 291     UNSERIALIZE_SCALAR(arbId);
 292     UNSERIALIZE_SCALAR(lowestPriorityOffset);
 293     UNSERIALIZE_ARRAY(redirTableArray, TableSize);
 294     UNSERIALIZE_ARRAY(pinStates, TableSize);
 295     for (int i = 0; i < TableSize; i++) {
 296         redirTable[i] = (RedirTableEntry)redirTableArray[i];
 297     }
 298 }
 299
 300 X86ISA::I82094AA *
 301 I82094AAParams::create()
 302 {
 303     return new X86ISA::I82094AA(this);
 304 }