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31 #include "arch/x86/interrupts.hh"
32 #include "arch/x86/intmessage.hh"
33 #include "cpu/base.hh"
34 #include "debug/I82094AA.hh"
35 #include "dev/x86/i82094aa.hh"
36 #include "dev/x86/i8259.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "sim/system.hh"
41 X86ISA::I82094AA::I82094AA(Params
*p
) : PioDevice(p
),
42 IntDev(this, p
->int_latency
),
43 latency(p
->pio_latency
), pioAddr(p
->pio_addr
),
44 extIntPic(p
->external_int_pic
), lowestPriorityOffset(0)
46 // This assumes there's only one I/O APIC in the system and since the apic
47 // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
50 assert(p
->apic_id
< 0xff);
51 initialApicId
= id
= p
->apic_id
;
54 RedirTableEntry entry
= 0;
56 for (int i
= 0; i
< TableSize
; i
++) {
57 redirTable
[i
] = entry
;
63 X86ISA::I82094AA::init()
65 // The io apic must register its address ranges on both its pio port
66 // via the piodevice init() function and its int port that it inherited
67 // from IntDev. Note IntDev is not a SimObject itself.
74 X86ISA::I82094AA::read(PacketPtr pkt
)
76 assert(pkt
->getSize() == 4);
77 Addr offset
= pkt
->getAddr() - pioAddr
;
80 pkt
->set
<uint32_t>(regSel
);
83 pkt
->set
<uint32_t>(readReg(regSel
));
86 panic("Illegal read from I/O APIC.\n");
88 pkt
->makeAtomicResponse();
93 X86ISA::I82094AA::write(PacketPtr pkt
)
95 assert(pkt
->getSize() == 4);
96 Addr offset
= pkt
->getAddr() - pioAddr
;
99 regSel
= pkt
->get
<uint32_t>();
102 writeReg(regSel
, pkt
->get
<uint32_t>());
105 panic("Illegal write to I/O APIC.\n");
107 pkt
->makeAtomicResponse();
112 X86ISA::I82094AA::writeReg(uint8_t offset
, uint32_t value
)
115 id
= bits(value
, 31, 24);
116 } else if (offset
== 0x1) {
117 // The IOAPICVER register is read only.
118 } else if (offset
== 0x2) {
119 arbId
= bits(value
, 31, 24);
120 } else if (offset
>= 0x10 && offset
<= (0x10 + TableSize
* 2)) {
121 int index
= (offset
- 0x10) / 2;
123 redirTable
[index
].topDW
= value
;
124 redirTable
[index
].topReserved
= 0;
126 redirTable
[index
].bottomDW
= value
;
127 redirTable
[index
].bottomReserved
= 0;
130 warn("Access to undefined I/O APIC register %#x.\n", offset
);
133 "Wrote %#x to I/O APIC register %#x .\n", value
, offset
);
137 X86ISA::I82094AA::readReg(uint8_t offset
)
142 } else if (offset
== 0x1) {
143 result
= ((TableSize
- 1) << 16) | APICVersion
;
144 } else if (offset
== 0x2) {
145 result
= arbId
<< 24;
146 } else if (offset
>= 0x10 && offset
<= (0x10 + TableSize
* 2)) {
147 int index
= (offset
- 0x10) / 2;
149 result
= redirTable
[index
].topDW
;
151 result
= redirTable
[index
].bottomDW
;
154 warn("Access to undefined I/O APIC register %#x.\n", offset
);
157 "Read %#x from I/O APIC register %#x.\n", result
, offset
);
162 X86ISA::I82094AA::signalInterrupt(int line
)
164 DPRINTF(I82094AA
, "Received interrupt %d.\n", line
);
165 assert(line
< TableSize
);
166 RedirTableEntry entry
= redirTable
[line
];
168 DPRINTF(I82094AA
, "Entry was masked.\n");
171 TriggerIntMessage message
= 0;
172 message
.destination
= entry
.dest
;
173 if (entry
.deliveryMode
== DeliveryMode::ExtInt
) {
175 message
.vector
= extIntPic
->getVector();
177 message
.vector
= entry
.vector
;
179 message
.deliveryMode
= entry
.deliveryMode
;
180 message
.destMode
= entry
.destMode
;
181 message
.level
= entry
.polarity
;
182 message
.trigger
= entry
.trigger
;
184 int numContexts
= sys
->numContexts();
185 if (message
.destMode
== 0) {
186 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
187 panic("Lowest priority delivery mode from the "
188 "IO APIC aren't supported in physical "
189 "destination mode.\n");
191 if (message
.destination
== 0xFF) {
192 for (int i
= 0; i
< numContexts
; i
++) {
196 apics
.push_back(message
.destination
);
199 for (int i
= 0; i
< numContexts
; i
++) {
200 Interrupts
*localApic
= sys
->getThreadContext(i
)->
201 getCpuPtr()->getInterruptController();
202 if ((localApic
->readReg(APIC_LOGICAL_DESTINATION
) >> 24) &
203 message
.destination
) {
204 apics
.push_back(localApic
->getInitialApicId());
207 if (message
.deliveryMode
== DeliveryMode::LowestPriority
&&
209 // The manual seems to suggest that the chipset just does
210 // something reasonable for these instead of actually using
211 // state from the local APIC. We'll just rotate an offset
212 // through the set of APICs selected above.
213 uint64_t modOffset
= lowestPriorityOffset
% apics
.size();
214 lowestPriorityOffset
++;
215 ApicList::iterator apicIt
= apics
.begin();
216 while (modOffset
--) {
218 assert(apicIt
!= apics
.end());
220 int selected
= *apicIt
;
222 apics
.push_back(selected
);
225 intPort
->sendMessage(apics
, message
,
226 sys
->getMemoryMode() == Enums::timing
);
231 X86ISA::I82094AA::raiseInterruptPin(int number
)
233 assert(number
< TableSize
);
234 if (!pinStates
[number
])
235 signalInterrupt(number
);
236 pinStates
[number
] = true;
240 X86ISA::I82094AA::lowerInterruptPin(int number
)
242 assert(number
< TableSize
);
243 pinStates
[number
] = false;
247 X86ISA::I82094AA::serialize(std::ostream
&os
)
249 uint64_t* redirTableArray
= (uint64_t*)redirTable
;
250 SERIALIZE_SCALAR(regSel
);
251 SERIALIZE_SCALAR(initialApicId
);
252 SERIALIZE_SCALAR(id
);
253 SERIALIZE_SCALAR(arbId
);
254 SERIALIZE_SCALAR(lowestPriorityOffset
);
255 SERIALIZE_ARRAY(redirTableArray
, TableSize
);
256 SERIALIZE_ARRAY(pinStates
, TableSize
);
260 X86ISA::I82094AA::unserialize(Checkpoint
*cp
, const std::string
§ion
)
262 uint64_t redirTableArray
[TableSize
];
263 UNSERIALIZE_SCALAR(regSel
);
264 UNSERIALIZE_SCALAR(initialApicId
);
265 UNSERIALIZE_SCALAR(id
);
266 UNSERIALIZE_SCALAR(arbId
);
267 UNSERIALIZE_SCALAR(lowestPriorityOffset
);
268 UNSERIALIZE_ARRAY(redirTableArray
, TableSize
);
269 UNSERIALIZE_ARRAY(pinStates
, TableSize
);
270 for (int i
= 0; i
< TableSize
; i
++) {
271 redirTable
[i
] = (RedirTableEntry
)redirTableArray
[i
];
276 I82094AAParams::create()
278 return new X86ISA::I82094AA(this);