src/dev/x86/i82094aa.hh

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __DEV_X86_I82094AA_HH__
  32 #define __DEV_X86_I82094AA_HH__
  33
  34 #include <map>
  35
  36 #include "base/bitunion.hh"
  37 #include "dev/x86/intdev.hh"
  38 #include "dev/io_device.hh"
  39 #include "params/I82094AA.hh"
  40
  41 namespace X86ISA
  42 {
  43
  44 class I8259;
  45 class Interrupts;
  46
  47 class I82094AA : public BasicPioDevice, public IntDevice
  48 {
  49   public:
  50     BitUnion64(RedirTableEntry)
  51         Bitfield<63, 32> topDW;
  52         Bitfield<55, 32> topReserved;
  53         Bitfield<31, 0> bottomDW;
  54         Bitfield<31, 17> bottomReserved;
  55         Bitfield<63, 56> dest;
  56         Bitfield<16> mask;
  57         Bitfield<15> trigger;
  58         Bitfield<14> remoteIRR;
  59         Bitfield<13> polarity;
  60         Bitfield<12> deliveryStatus;
  61         Bitfield<11> destMode;
  62         Bitfield<10, 8> deliveryMode;
  63         Bitfield<7, 0> vector;
  64     EndBitUnion(RedirTableEntry)
  65
  66   protected:
  67     I8259 * extIntPic;
  68
  69     uint8_t regSel;
  70     uint8_t initialApicId;
  71     uint8_t id;
  72     uint8_t arbId;
  73
  74     uint64_t lowestPriorityOffset;
  75
  76     static const uint8_t TableSize = 24;
  77     // This implementation is based on version 0x11, but 0x14 avoids having
  78     // to deal with the arbitration and APIC bus guck.
  79     static const uint8_t APICVersion = 0x14;
  80
  81     RedirTableEntry redirTable[TableSize];
  82     bool pinStates[TableSize];
  83
  84   public:
  85     typedef I82094AAParams Params;
  86
  87     const Params *
  88     params() const
  89     {
  90         return dynamic_cast<const Params *>(_params);
  91     }
  92
  93     I82094AA(Params *p);
  94
  95     void init();
  96
  97     Tick read(PacketPtr pkt);
  98     Tick write(PacketPtr pkt);
  99
 100     AddrRangeList getIntAddrRange() const;
 101
 102     void writeReg(uint8_t offset, uint32_t value);
 103     uint32_t readReg(uint8_t offset);
 104
 105     BaseMasterPort &getMasterPort(const std::string &if_name,
 106                                   PortID idx = InvalidPortID);
 107
 108     Tick recvResponse(PacketPtr pkt) M5_ATTR_OVERRIDE;
 109
 110     void signalInterrupt(int line);
 111     void raiseInterruptPin(int number);
 112     void lowerInterruptPin(int number);
 113
 114     void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
 115     void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
 116 };
 117
 118 } // namespace X86ISA
 119
 120 #endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__