X86: Record the initial APIC ID which identifies an APIC in M5.
[gem5.git] / src / dev / x86 / i82094aa.hh
1 /*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #ifndef __DEV_X86_I82094AA_HH__
32 #define __DEV_X86_I82094AA_HH__
33
34 #include "base/bitunion.hh"
35 #include "base/range_map.hh"
36 #include "dev/io_device.hh"
37 #include "dev/x86/intdev.hh"
38 #include "params/I82094AA.hh"
39
40 namespace X86ISA
41 {
42
43 class I8259;
44
45 class I82094AA : public PioDevice, public IntDev
46 {
47 public:
48 BitUnion64(RedirTableEntry)
49 Bitfield<63, 32> topDW;
50 Bitfield<55, 32> topReserved;
51 Bitfield<31, 0> bottomDW;
52 Bitfield<31, 17> bottomReserved;
53 Bitfield<63, 56> dest;
54 Bitfield<16> mask;
55 Bitfield<15> trigger;
56 Bitfield<14> remoteIRR;
57 Bitfield<13> polarity;
58 Bitfield<12> deliveryStatus;
59 Bitfield<11> destMode;
60 Bitfield<10, 8> deliveryMode;
61 Bitfield<7, 0> vector;
62 EndBitUnion(RedirTableEntry)
63
64 protected:
65 Tick latency;
66 Addr pioAddr;
67
68 I8259 * extIntPic;
69
70 uint8_t regSel;
71 uint8_t initialApicId;
72 uint8_t id;
73 uint8_t arbId;
74
75 static const uint8_t TableSize = 24;
76 // This implementation is based on version 0x11, but 0x14 avoids having
77 // to deal with the arbitration and APIC bus guck.
78 static const uint8_t APICVersion = 0x14;
79
80 RedirTableEntry redirTable[TableSize];
81 bool pinStates[TableSize];
82
83 public:
84 typedef I82094AAParams Params;
85
86 const Params *
87 params() const
88 {
89 return dynamic_cast<const Params *>(_params);
90 }
91
92 I82094AA(Params *p);
93
94 Tick read(PacketPtr pkt);
95 Tick write(PacketPtr pkt);
96
97 void addressRanges(AddrRangeList &range_list)
98 {
99 range_list.clear();
100 range_list.push_back(RangeEx(pioAddr, pioAddr + 4));
101 range_list.push_back(RangeEx(pioAddr + 16, pioAddr + 20));
102 }
103
104 void getIntAddrRange(AddrRangeList &range_list)
105 {
106 range_list.clear();
107 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
108 x86InterruptAddress(initialApicId, 0) +
109 PhysAddrAPICRangeSize));
110 }
111
112 void writeReg(uint8_t offset, uint32_t value);
113 uint32_t readReg(uint8_t offset);
114
115 Port *getPort(const std::string &if_name, int idx = -1)
116 {
117 if (if_name == "int_port")
118 return intPort;
119 return PioDevice::getPort(if_name, idx);
120 }
121
122 void signalInterrupt(int line);
123 void raiseInterruptPin(int number);
124 void lowerInterruptPin(int number);
125 };
126
127 }; // namespace X86ISA
128
129 #endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__