src/dev/x86/i8259.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "dev/x86/i8259.hh"
  30
  31 #include "base/bitfield.hh"
  32 #include "debug/I8259.hh"
  33 #include "dev/x86/i82094aa.hh"
  34 #include "mem/packet.hh"
  35 #include "mem/packet_access.hh"
  36
  37 X86ISA::I8259::I8259(Params * p)
  38     : BasicPioDevice(p, 2),
  39       latency(p->pio_latency),
  40       mode(p->mode), slave(p->slave),
  41       IRR(0), ISR(0), IMR(0),
  42       readIRR(true), initControlWord(0), autoEOI(false)
  43 {
  44     for (int i = 0; i < p->port_output_connection_count; i++) {
  45         output.push_back(new IntSourcePin<I8259>(
  46                     csprintf("%s.output[%d]", name(), i), i, this));
  47     }
  48
  49     int in_count = p->port_inputs_connection_count;
  50     panic_if(in_count >= NumLines,
  51             "I8259 only supports 8 inputs, but there are %d.", in_count);
  52     for (int i = 0; i < in_count; i++) {
  53         inputs.push_back(new IntSinkPin<I8259>(
  54                     csprintf("%s.inputs[%d]", name(), i), i, this));
  55     }
  56
  57     for (bool &state: pinStates)
  58         state = false;
  59 }
  60
  61 void
  62 X86ISA::I8259::init()
  63 {
  64     BasicPioDevice::init();
  65
  66     for (auto *input: inputs)
  67         pinStates[input->getId()] = input->state();
  68 }
  69
  70 Tick
  71 X86ISA::I8259::read(PacketPtr pkt)
  72 {
  73     assert(pkt->getSize() == 1);
  74     switch(pkt->getAddr() - pioAddr)
  75     {
  76       case 0x0:
  77         if (readIRR) {
  78             DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
  79             pkt->setLE(IRR);
  80         } else {
  81             DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
  82             pkt->setLE(ISR);
  83         }
  84         break;
  85       case 0x1:
  86         DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
  87         pkt->setLE(IMR);
  88         break;
  89     }
  90     pkt->makeAtomicResponse();
  91     return latency;
  92 }
  93
  94 Tick
  95 X86ISA::I8259::write(PacketPtr pkt)
  96 {
  97     assert(pkt->getSize() == 1);
  98     uint8_t val = pkt->getLE<uint8_t>();
  99     switch (pkt->getAddr() - pioAddr) {
 100       case 0x0:
 101         if (bits(val, 4)) {
 102             DPRINTF(I8259, "Received initialization command word 1.\n");
 103             IMR = 0;
 104             edgeTriggered = bits(val, 3);
 105             DPRINTF(I8259, "%s triggered mode.\n",
 106                     edgeTriggered ? "Edge" : "Level");
 107             cascadeMode = !bits(val, 1);
 108             DPRINTF(I8259, "%s mode.\n",
 109                     cascadeMode ? "Cascade" : "Single");
 110             expectICW4 = bits(val, 0);
 111             if (!expectICW4) {
 112                 autoEOI = false;
 113             }
 114             initControlWord = 1;
 115             DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
 116         } else if (bits(val, 4, 3) == 0) {
 117             DPRINTF(I8259, "Received operation command word 2.\n");
 118             switch (bits(val, 7, 5)) {
 119               case 0x0:
 120                 DPRINTF(I8259,
 121                         "Subcommand: Rotate in auto-EOI mode (clear).\n");
 122                 break;
 123               case 0x1:
 124                 {
 125                     int line = findMsbSet(ISR);
 126                     DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
 127                             line);
 128                     handleEOI(line);
 129                 }
 130                 break;
 131               case 0x2:
 132                 DPRINTF(I8259, "Subcommand: No operation.\n");
 133                 break;
 134               case 0x3:
 135                 {
 136                     int line = bits(val, 2, 0);
 137                     DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
 138                             line);
 139                     handleEOI(line);
 140                 }
 141                 break;
 142               case 0x4:
 143                 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
 144                 break;
 145               case 0x5:
 146                 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
 147                 break;
 148               case 0x6:
 149                 DPRINTF(I8259, "Subcommand: Set priority command.\n");
 150                 DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
 151                         bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
 152                 break;
 153               case 0x7:
 154                 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
 155                 DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
 156                         bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
 157                 break;
 158             }
 159         } else if (bits(val, 4, 3) == 1) {
 160             DPRINTF(I8259, "Received operation command word 3.\n");
 161             if (bits(val, 7)) {
 162                 DPRINTF(I8259, "%s special mask mode.\n",
 163                         bits(val, 6) ? "Set" : "Clear");
 164             }
 165             if (bits(val, 1)) {
 166                 readIRR = bits(val, 0);
 167                 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
 168             }
 169         }
 170         break;
 171       case 0x1:
 172         switch (initControlWord) {
 173           case 0x0:
 174             DPRINTF(I8259, "Received operation command word 1.\n");
 175             DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
 176             IMR = val;
 177             break;
 178           case 0x1:
 179             DPRINTF(I8259, "Received initialization command word 2.\n");
 180             vectorOffset = val & ~mask(3);
 181             DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
 182                     vectorOffset, vectorOffset | mask(3));
 183             if (cascadeMode) {
 184                 initControlWord++;
 185             } else {
 186                 cascadeBits = 0;
 187                 initControlWord = 0;
 188             }
 189             break;
 190           case 0x2:
 191             DPRINTF(I8259, "Received initialization command word 3.\n");
 192             if (mode == Enums::I8259Master) {
 193                 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
 194                         bits(val, 0) ? " 0" : "",
 195                         bits(val, 1) ? " 1" : "",
 196                         bits(val, 2) ? " 2" : "",
 197                         bits(val, 3) ? " 3" : "",
 198                         bits(val, 4) ? " 4" : "",
 199                         bits(val, 5) ? " 5" : "",
 200                         bits(val, 6) ? " 6" : "",
 201                         bits(val, 7) ? " 7" : "");
 202                 cascadeBits = val;
 203             } else {
 204                 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
 205                 cascadeBits = val & mask(3);
 206             }
 207             if (expectICW4)
 208                 initControlWord++;
 209             else
 210                 initControlWord = 0;
 211             break;
 212           case 0x3:
 213             DPRINTF(I8259, "Received initialization command word 4.\n");
 214             if (bits(val, 4)) {
 215                 DPRINTF(I8259, "Special fully nested mode.\n");
 216             } else {
 217                 DPRINTF(I8259, "Not special fully nested mode.\n");
 218             }
 219             if (bits(val, 3) == 0) {
 220                 DPRINTF(I8259, "Nonbuffered.\n");
 221             } else if (bits(val, 2) == 0) {
 222                 DPRINTF(I8259, "Buffered.\n");
 223             } else {
 224                 DPRINTF(I8259, "Unrecognized buffer mode.\n");
 225             }
 226             autoEOI = bits(val, 1);
 227             DPRINTF(I8259, "%s End Of Interrupt.\n",
 228                     autoEOI ? "Automatic" : "Normal");
 229
 230             DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
 231             initControlWord = 0;
 232             break;
 233         }
 234         break;
 235     }
 236     pkt->makeAtomicResponse();
 237     return latency;
 238 }
 239
 240 void
 241 X86ISA::I8259::handleEOI(int line)
 242 {
 243     ISR &= ~(1 << line);
 244     // There may be an interrupt that was waiting which can
 245     // now be sent.
 246     if (IRR)
 247         requestInterrupt(findMsbSet(IRR));
 248 }
 249
 250 void
 251 X86ISA::I8259::requestInterrupt(int line)
 252 {
 253     if (bits(ISR, 7, line) == 0) {
 254         if (!output.empty()) {
 255             DPRINTF(I8259, "Propogating interrupt.\n");
 256             for (auto *wire: output) {
 257                 wire->raise();
 258                 //XXX This is a hack.
 259                 wire->lower();
 260             }
 261         } else {
 262             warn("Received interrupt but didn't have "
 263                     "anyone to tell about it.\n");
 264         }
 265     }
 266 }
 267
 268 void
 269 X86ISA::I8259::signalInterrupt(int line)
 270 {
 271     DPRINTF(I8259, "Interrupt requested for line %d.\n", line);
 272     if (line >= NumLines)
 273         fatal("Line number %d doesn't exist. The max is %d.\n",
 274                 line, NumLines - 1);
 275     if (bits(IMR, line)) {
 276         DPRINTF(I8259, "Interrupt %d was masked.\n", line);
 277     } else {
 278         IRR |= 1 << line;
 279         requestInterrupt(line);
 280     }
 281 }
 282
 283 void
 284 X86ISA::I8259::raiseInterruptPin(int number)
 285 {
 286     DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number);
 287     if (number >= NumLines)
 288         fatal("Line number %d doesn't exist. The max is %d.\n",
 289                 number, NumLines - 1);
 290     if (!pinStates[number])
 291         signalInterrupt(number);
 292     pinStates[number] = true;
 293 }
 294
 295 void
 296 X86ISA::I8259::lowerInterruptPin(int number)
 297 {
 298     DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number);
 299     if (number >= NumLines)
 300         fatal("Line number %d doesn't exist. The max is %d.\n",
 301                 number, NumLines - 1);
 302     pinStates[number] = false;
 303 }
 304
 305 int
 306 X86ISA::I8259::getVector()
 307 {
 308     /*
 309      * This code only handles one slave. Since that's how the PC platform
 310      * always uses the 8259 PIC, there shouldn't be any need for more. If
 311      * there -is- a need for more for some reason, "slave" can become a
 312      * vector of slaves.
 313      */
 314     int line = findMsbSet(IRR);
 315     IRR &= ~(1 << line);
 316     DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
 317     if (autoEOI) {
 318         handleEOI(line);
 319     } else {
 320         ISR |= 1 << line;
 321     }
 322     if (slave && bits(cascadeBits, line)) {
 323         DPRINTF(I8259, "Interrupt was from slave who will "
 324                 "provide the vector.\n");
 325         return slave->getVector();
 326     }
 327     return line | vectorOffset;
 328 }
 329
 330 void
 331 X86ISA::I8259::serialize(CheckpointOut &cp) const
 332 {
 333     SERIALIZE_ARRAY(pinStates, NumLines);
 334     SERIALIZE_ENUM(mode);
 335     SERIALIZE_SCALAR(IRR);
 336     SERIALIZE_SCALAR(ISR);
 337     SERIALIZE_SCALAR(IMR);
 338     SERIALIZE_SCALAR(vectorOffset);
 339     SERIALIZE_SCALAR(cascadeMode);
 340     SERIALIZE_SCALAR(cascadeBits);
 341     SERIALIZE_SCALAR(edgeTriggered);
 342     SERIALIZE_SCALAR(readIRR);
 343     SERIALIZE_SCALAR(expectICW4);
 344     SERIALIZE_SCALAR(initControlWord);
 345     SERIALIZE_SCALAR(autoEOI);
 346 }
 347
 348 void
 349 X86ISA::I8259::unserialize(CheckpointIn &cp)
 350 {
 351     UNSERIALIZE_ARRAY(pinStates, NumLines);
 352     UNSERIALIZE_ENUM(mode);
 353     UNSERIALIZE_SCALAR(IRR);
 354     UNSERIALIZE_SCALAR(ISR);
 355     UNSERIALIZE_SCALAR(IMR);
 356     UNSERIALIZE_SCALAR(vectorOffset);
 357     UNSERIALIZE_SCALAR(cascadeMode);
 358     UNSERIALIZE_SCALAR(cascadeBits);
 359     UNSERIALIZE_SCALAR(edgeTriggered);
 360     UNSERIALIZE_SCALAR(readIRR);
 361     UNSERIALIZE_SCALAR(expectICW4);
 362     UNSERIALIZE_SCALAR(initControlWord);
 363     UNSERIALIZE_SCALAR(autoEOI);
 364 }
 365
 366 X86ISA::I8259 *
 367 I8259Params::create()
 368 {
 369     return new X86ISA::I8259(this);
 370 }