src/dev/x86/intdev.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2008 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #ifndef __DEV_X86_INTDEV_HH__
  44 #define __DEV_X86_INTDEV_HH__
  45
  46 #include <cassert>
  47 #include <list>
  48 #include <string>
  49
  50 #include "arch/x86/intmessage.hh"
  51 #include "mem/tport.hh"
  52 #include "sim/sim_object.hh"
  53
  54 namespace X86ISA
  55 {
  56
  57 template <class Device>
  58 class IntSlavePort : public SimpleTimingPort
  59 {
  60     Device * device;
  61
  62   public:
  63     IntSlavePort(const std::string& _name, SimObject* _parent,
  64                  Device* dev) :
  65         SimpleTimingPort(_name, _parent), device(dev)
  66     {
  67     }
  68
  69     AddrRangeList
  70     getAddrRanges() const
  71     {
  72         return device->getIntAddrRange();
  73     }
  74
  75     Tick
  76     recvAtomic(PacketPtr pkt)
  77     {
  78         panic_if(pkt->cmd != MemCmd::WriteReq,
  79                 "%s received unexpected command %s from %s.\n",
  80                 name(), pkt->cmd.toString(), getPeer());
  81         pkt->headerDelay = pkt->payloadDelay = 0;
  82         return device->recvMessage(pkt);
  83     }
  84 };
  85
  86 typedef std::list<int> ApicList;
  87
  88 template <class Device>
  89 class IntMasterPort : public QueuedMasterPort
  90 {
  91     ReqPacketQueue reqQueue;
  92     SnoopRespPacketQueue snoopRespQueue;
  93
  94     Device* device;
  95     Tick latency;
  96
  97   public:
  98     IntMasterPort(const std::string& _name, SimObject* _parent,
  99                   Device* dev, Tick _latency) :
 100         QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
 101         reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
 102         device(dev), latency(_latency)
 103     {
 104     }
 105
 106     bool
 107     recvTimingResp(PacketPtr pkt) override
 108     {
 109         return device->recvResponse(pkt);
 110     }
 111
 112     // This is x86 focused, so if this class becomes generic, this would
 113     // need to be moved into a subclass.
 114     void
 115     sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing)
 116     {
 117         for (auto id: apics) {
 118             Addr addr = x86InterruptAddress(id, TriggerIntOffset);
 119             PacketPtr pkt = buildIntPacket(addr, message);
 120             if (timing) {
 121                 schedTimingReq(pkt, curTick() + latency);
 122                 // The target handles cleaning up the packet in timing mode.
 123             } else {
 124                 // ignore the latency involved in the atomic transaction
 125                 sendAtomic(pkt);
 126                 assert(pkt->isResponse());
 127                 // also ignore the latency in handling the response
 128                 device->recvResponse(pkt);
 129             }
 130         }
 131     }
 132 };
 133
 134 } // namespace X86ISA
 135
 136 #endif //__DEV_X86_INTDEV_HH__